LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 151
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LPC47M107S-MS
Manufacturer Part Number
LPC47M107S-MS
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LPC47M107S-MS.pdf
(188 pages)
Specifications of LPC47M107S-MS
Pin Count
100
Lead Free Status / RoHS Status
Compliant
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Note 2: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O
Note 3: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Note 4: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device
LOGICAL
NUMBER
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or
clears the other.
map, then read or write is not valid and is ignored.
3 and 5 is 0x04.
DEVICE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
Serial Port 1
Serial Port 2
Game Port
LOGICAL
Reserved
Reserved
Reserved
Reserved
DEVICE
Parallel
KYBD
FDC
Table 65 - I/O Base Address Configuration Register Description
Port
REGISTER
0x60,0x61
0x60,0x61
0x60,0x61
0x60,0x61
0x60,0x61
INDEX
n/a
n/a
n/a
n/a
n/a
Page 151
the base address is on an 8-
ON 8 BYTE BOUNDARIES
ON 4 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
EPP is only available when
Fixed Base Address: 60,64
(all modes supported,
on 1 byte boundaries
(EPP Not supported)
[0x0100:0x0FFC]
[0x0100:0x0FFF]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
Not Relocatable
byte boundary)
BASE I/O
(NOTE 1)
RANGE
n/a
n/a
n/a
n/a
or
+0 : SRA
+1 : SRB
+2 : DOR
+3 : TSR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
n/a
n/a
+0 : Data/ecpAfifo
+1 : Status
+2 : Control
+400h :
cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
+402h : ecr
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
n/a
+0 : Data Register
+4 : Command/Status
Reg.
n/a
+00: Game Port Register
BASE OFFSETS
FIXED
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