LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 87

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1,
followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished
by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0.
DMA Mode - Transfers from the FIFO to the Host
(Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the
chip continues to request more data from the peripheral.)
The ECP requests a DMA cycle whenever there is data in the FIFO. The DMA controller must respond to the request by
reading data from the FIFO. The ECP stops requesting DMA cycles when the FIFO becomes empty or when a TC cycle
is received, indicating that no more data is required. If the ECP stops requesting DMA cycles due to the FIFO going
empty, then a DMA cycle is requested again as soon as there is one byte in the FIFO. If the ECP stops requesting DMA
cycles due to the TC cycle, then a DMA cycle is requested again when there is one byte in the FIFO, and serviceIntr has
been re-enabled.
Programmed I/O Mode or Non-DMA Mode
The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine
the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or
to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets
dmaEn to 0 and serviceIntr to 0.
The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty or
fill the FIFO using the appropriate direction and mode.
Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.
Programmed I/O - Transfers from the FIFO to the Host
In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO.
If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be
read from the FIFO in a single burst.
ReadIntrThreshold =
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16-
<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO). The host must
respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of
the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16-
<threshold>) bytes may be read from the FIFO in a single burst.
Programmed I/O - Transfers from the Host to the FIFO
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in
the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read.
Otherwise it may be filled with writeIntrThreshold bytes.
writeIntrThreshold =
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to <threshold>.
(If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The host must
respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single
burst, otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a single burst. This process is
repeated until the last byte is transferred into the FIFO.
(16-<threshold>) data bytes in FIFO
(16-<threshold>) free bytes in FIFO
Page 87