LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 31

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 - 6 UNDEFINED
Always read as a logic "0"
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
CONFIGURATION CONTROL REGISTER (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values.
BIT 2 - 7 RESERVED
Should be set to a logical "0"
PS/2 Model 30 Mode
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register
mode. Unaffected by software reset.
BIT 3 - 7 RESERVED
Should be set to a logical "0"
Table 9 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the
DOR and the DSR resets.
RESET
COND.
RESET
COND.
N/A
N/A
7
7
N/A
N/A
6
6
N/A
N/A
5
5
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N/A
N/A
4
4
N/A
N/A
3
3
NOPREC DRATE
N/A
N/A
2
2
DRATE
SEL1
SEL1
1
1
1
1
DRATE
DRATE
SEL0
SEL0
0
0
0
0