PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 63

• Manufacturer Part Number: PIC18LF27J13T-I/SO
• Description: 28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J13T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A series resistor between RA0 and the external
capacitor provides overcurrent protection for the
RA0/AN0/C1INA/ULPWU/RP0 pin and can allow for
software calibration of the time-out (see Figure 4-9).
FIGURE 4-9:
A timer can be used to measure the charge time and
discharge time of the capacitor. The charge time can
then be adjusted to provide the desired interrupt delay.
This technique will compensate for the affects of
temperature, voltage and component accuracy. The
ULPWU peripheral can also be configured as a simple
Programmable
temperature sensor.
TABLE 4-2:
 2010 Microchip Technology Inc.
Register
PMDIS3
PMDIS2
PMDIS1
PMDIS0
Note 1:
Note:
2:
ECCP3MD
CCP10MD
PSPMD
Not implemented on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13).
To prevent accidental RTCC changes, the RTCCMD bit is normally locked. Use the following unlock sequence (with
interrupts disabled) to successfully modify the RTCCMD bit:
1. Write 55h to EECON2.
2. Write 0AAh to EECON2.
3. Immediately write the modified RTCCMD setting to PMDIS1.
RA0
For more information, refer to AN879,
“Using the Microchip Ultra Low-Power
Wake-up
(DS00879).
Bit 7
—
(1)
Low-Voltage
LOW-POWER MODE REGISTERS
SERIAL RESISTOR
ECCP2MD
CTMUMD
CCP9MD
TMR8MD
Module”
Bit 6
R
1
Detect
RTCCMD
ECCP1MD
application
CCP8MD
C
Bit 5
1
—
(2)
(LVD)
UART2MD
CCP7MD
TMR6MD
TMR4MD
note
Bit 4
Preliminary
or
UART1MD
CCP6MD
TMR5MD
TMR3MD
PIC18F47J13 FAMILY
Bit 3
4.8
All peripheral modules (except for I/O ports) also have
a second control bit that can disable their functionality.
These bits, known as the Peripheral Module Disable
(PMD) bits, are generically named “xxxMD” (using
“xxx” as the mnemonic version of the module’s name).
These bits are located in the PMDISx special function
registers. In contrast to the module enable bits (gener-
ically named “xxxEN” and located in bit position seven
of the control registers), the PMD bits must be set (= 1)
to disable the modules.
While the PMD and module enable bits both disable a
peripheral’s functionality, the PMD bit completely shuts
down the peripheral, effectively powering down all
circuits and removing all clock sources. This has the
additional effect of making any of the module’s control
and buffer registers, mapped in the SFR space,
unavailable for operations. Essentially, the peripheral
ceases to exist until the PMD bit is cleared.
This differs from using the module enable bit, which
allows the peripheral to be reconfigured and buffer
registers preloaded, even when the peripheral’s
operations are disabled.
The PMD bits are most useful in highly power-sensitive
applications. In these cases, the bits can be set before
the main body of the application to remove peripherals
that will not be needed at all.
CMP3MD
TMR2MD
CCP5MD
Peripheral Module Disable
SPI2MD
Bit 2
CMP2MD
CCP4MD
TMR1MD
SP11MD
Bit 1
CMP1MD
ADCMD
Bit 0
—
—
DS39974A-page 63
0000 000–
–0–0 0000
0000 000–
0000 0000
POR, BOR
Value on