PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 152

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PIC18LF27J13T-I/SO

Manufacturer Part Number
PIC18LF27J13T-I/SO
Description
28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets

Specifications of PIC18LF27J13T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F47J13 FAMILY
TABLE 10-7:
TABLE 10-8:
DS39974A-page 152
RC5/SDO1/
RP16
RC6/CCP9/
PMA5/TX1/
CK1/RP17
RC7/CCP10/
PMA4/RX1/
DT1/RP18
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
PORTC
LATC
TRISC
ANCON1
CM2CON
RTCCFG
Name
Pin
input/output; I
overridden for this option)
This bit is only available on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and
PIC18LF47J13).
PORTC I/O SUMMARY (CONTINUED)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
TRISC7
VBGEN
RTCEN
Function
LATC7
PMA5
PMA4
Bit 7
CON
CCP10
RC7
SDO1
CCP9
RP16
RP17
RP18
RC5
RC6
CK1
RC7
RX1
TX1
DT1
2
(1)
(1)
C/SMB = I
TRISC6
Setting
LATC6
Bit 6
COE
TRIS
RC6
0
x
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
x
1
1
0
1
0
2
C/SMBus input buffer; x = Don’t care (TRISx bit does not affect port direction or is
RTCWREN RTCSYNC HALFSEC
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
1
I
I
I
I
I
I
I
I
I
I
TRISC5
LATC5
CPOL
Bit 5
RC5
ST/TTL/
ST/TTL Parallel Master Port io_addr_in<5>.
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
Preliminary
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
PCFG12
EVPOL1
TRISC4
LATC4
PORTC<5> data output.
SPI data output (MSSP1 module).
Remappable Peripheral Pin 16 input.
Remappable Peripheral Pin 16 output.
PORTC<6> data input.
LATC<6> data output.
Capture input.
Compare/PWM output.
Parallel Master Port address.
Asynchronous serial transmit data output (EUSART module);
takes priority over port data. User must configure as an output.
Synchronous serial clock input (EUSART module).
Synchronous serial clock output (EUSART module); takes
priority over port data.
Remappable Peripheral Pin 17 input.
Remappable Peripheral Pin 17 output.
PORTC<7> data input.
LATC<7> data output.
Capture input.
Compare/PWM output.
Parallel Master Port address.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data input (EUSART module). User
must configure as an input.
Synchronous serial data output (EUSART module); takes
priority over port data.
Remappable Peripheral Pin 18 input.
Remappable Peripheral Pin 18 output.
Bit 4
RC4
EVPOL0
PCFG11
TRISC3
LATC3
Bit 3
RC3
Description
PCFG10
TRISC2
RTCOE
LATC2
CREF
Bit 2
RC2
 2010 Microchip Technology Inc.
RTCPTR1 RTCPTR0
TRISC1
PCFG9
LATC1
CCH1
Bit 1
RC1
TRISC0
PCFG8
LATC0
CCH0
Bit 0
RC0

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