PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 425

• Manufacturer Part Number: PIC18LF27J13T-I/SO
• Description: 28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J13T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 27-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h)
TABLE 27-3:
 2010 Microchip Technology Inc.
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
REGSLP
R/W-1
Name
2:
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Not available on devices where the on-chip voltage regulator is disabled (“LF” devices).
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator is active even in Sleep mode
LVDSTAT: Low-Voltage Detect Status bit
1 = V
0 = V
ULPLVL: Ultra Low-Power Wake-up Output bit (not valid unless ULPEN = 1)
1 = Voltage on RA0 > ~0.5V
0 = Voltage on RA0 < ~0.5V
VBGOE: Band Gap Reference Voltage (VBG) Output Enable bit
1 = Band gap reference output is enabled on the RA1 pin
0 = Band gap reference output is disabled
DS: Deep Sleep Wake-up Status bit (used in conjunction with RCON, POR and BOR bits to determine
Reset source)
1 = If the last exit from Reset was caused by a normal wake-up from Deep Sleep
0 = If the last exit from Reset was not due to a wake-up from Deep Sleep
ULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = Ultra low-power wake-up module is enabled; ULPLVL bit indicates the comparator output
0 = Ultra low-power wake-up module is disabled
ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit
1 = Ultra low-power wake-up current sink is enabled (if ULPEN = 1)
0 = Ultra low-power wake-up current sink is disabled
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
LVDSTAT
REGSLP
SUMMARY OF WATCHDOG TIMER REGISTERS
IPEN
Bit 7
R-x
DDCORE
DDCORE
(2)
> 2.45V nominal
< 2.45V nominal
(2)
LVDSTAT
W = Writable bit
‘1’ = Bit is set
Bit 6
ULPLVL
—
R-x
ULPLVL
Bit 5
CM
VBGOE
R/W-0
Preliminary
(2)
VBGOE
Bit 4
RI
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F47J13 FAMILY
DS
R-0
(2)
Bit 3
DS
TO
(1)
ULPEN
R/W-0
ULPEN
Bit 2
PD
x = Bit is unknown
ULPSINK
R/W-0
ULPSINK
Bit 1
POR
DS39974A-page 425
SWDTEN
SWDTEN
R/W-0
Bit 0
BOR
bit 0
(1)