PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 412

• Manufacturer Part Number: PIC18LF27J13T-I/SO
• Description: 28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J13T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F47J13 FAMILY
REGISTER 26-3:
REGISTER 26-4:
DS39974A-page 412
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-2
bit 1
bit 0
CTMUDS
ITRIM5
R/W-0
R/W-0
ITRIM<5:0>: Current Source Trim bits
011111 = Maximum positive change (+62% typ.) from nominal current
011110
.
.
.
000001 = Minimum positive change (+2% typ.) from nominal current
000000 = Nominal current output specified by IRNG<1:0>
111111 = Minimum negative change (-2% typ.) from nominal current
.
.
.
100010
100001 = Maximum negative change (-62% typ.) from nominal current
IRNG<1:0>: Current Source Range Select bits
11 = 100  Base current
10 = 10  Base current
01 = Base current level (0.55 A nominal)
00 = Current source disabled
CTMUDS: CTMU Pulse Delay Enable bit
1 = Pulse delay input for CTMU enabled on pin RA1
Unimplemented: Read as ‘0’
SPI2OD: SPI2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
SPI1OD: SPI1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
ITRIM4
R/W-0
U-0
—
CTMUICON: CTMU CURRENT CONTROL REGISTER (ACCESS FB1h)
ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
ITRIM3
R/W-0
U-0
—
ITRIM2
R/W-0
U-0
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ITRIM1
R/W-0
U-0
—
ITRIM0
R/W-0
U-0
—
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
SPI2OD
IRNG1
R/W-0
R/W-0
SPI1OD
IRNG0
R/W-0
R/W-0
bit 0
bit 0