PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 216

• Manufacturer Part Number: PIC18LF27J13T-I/SO
• Description: 28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J13T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F47J13 FAMILY
13.8.2
The Timer1 gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSSx bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
TABLE 13-4:
13.8.2.1
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
13.8.2.2
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
FIGURE 13-5:
DS39974A-page 216
T1GSS<1:0>
TMR1GE
T1GPOL
T1GVAL
T1G_IN
T1GTM
Timer1
00
01
10
11
T1CKI
TIMER1 GATE SOURCE
SELECTION
T1G Pin Gate Operation
Timer2 Match Gate Operation
Timer1 Gate Pin
TMR2 matches PR2
Comparator 1 output
Comparator 2 output
TIMER1 GATE SOURCES
N
TIMER1 GATE TOGGLE MODE
Timer1 Gate Source
N + 1 N + 2 N + 3
Preliminary
occurs, a low-to-high pulse will automatically be
generated and internally supplied to the Timer1 gate
circuitry. The pulse remains high for one instruction
cycle and returns to low until the next match.
When T1GPOL = 1, Timer1 increments for a single
instruction cycle following TMR2 matching PR2. With
T1GPOL = 0, Timer1 increments except during the
cycle following the match.
13.8.3
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 13-5 for timing details.
The T1GVAL bit will indicate when the Toggled mode is
active and the timer is counting.
The Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
N + 4
TIMER1 GATE TOGGLE MODE
N + 5 N + 6 N + 7
 2010 Microchip Technology Inc.
N + 8