PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 142

• Manufacturer Part Number: PIC18LF27J13T-I/SO
• Description: 28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J13T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F47J13 FAMILY
REGISTER 10-2:
REGISTER 10-3:
DS39974A-page 142
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3
bit 2
bit 1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-2
bit 1
bit 0
CTMUDS
R/W-0
U-0
—
Unimplemented: Read as ‘0’
CCP10OD: CCP10 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
CCP9OD: CCP9 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
U2OD: USART2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
U1OD: USART1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
CTMUDS: CTMU Pulse Delay Enable bit
1 = Pulse delay input for CTMU enabled on pin, RA1
Unimplemented: Read as ‘0’
SPI2OD: SPI2 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
SPI1OD: SPI1 Open-Drain Output Enable bit
1 = Open-drain capability is enabled
0 = Open-drain capability is disabled
U-0
U-0
—
—
ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h)
ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
—
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCP10OD
R/W-0
U-0
—
CCP9OD
R/W-0
U-0
—
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
SPI2OD
R/W-0
U2OD
R/W-0
SPI1OD
R/W-0
U1OD
R/W-0
bit 0
bit 0