PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 201

• Manufacturer Part Number: PIC18LF27J13T-I/SO
• Description: 28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J13T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.4
This section introduces some potential applications for
the PMP module.
FIGURE 11-27:
11.4.2
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 11-28 provides an example of a
memory or peripheral that is partially multiplexed with
FIGURE 11-28:
FIGURE 11-29:
 2010 Microchip Technology Inc.
Application Examples
PIC18F
PIC18F
PIC18F
PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
PMD<7:0>
PMD<7:0>
PMD<7:0>
PMALH
PMALL
PMALL
PMWR
PMWR
PMRD
PMALL
PMRD
PMCS
PMCS
PMWR
PMCS
PMRD
MULTIPLEXED ADDRESSING APPLICATION EXAMPLE
EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
AD<7:0>
ALE
CS
RD
WR
373
373
373
Parallel Peripheral
Preliminary
A<15:8>
A<7:0>
D<7:0>
D<7:0>
A<7:0>
PIC18F47J13 FAMILY
11.4.1
Figure 11-27 demonstrates the hookup of a memory or
another addressable peripheral in Full Multiplex mode.
Consequently, this mode achieves the best pin saving
from the microcontroller perspective. However, for this
configuration, there needs to be some external latches
to maintain the address.
an external latch. If the peripheral has internal latches,
as displayed in Figure 11-29, then no extra circuitry is
required except for the peripheral itself.
MULTIPLEXED MEMORY OR
PERIPHERAL
A<7:0>
D<7:0>
CE
A<13:0>
D<7:0>
CE
OE
OE
WR
WR
Address Bus
Data Bus
Control Lines
Address Bus
Data Bus
Control Lines
Address Bus
Data Bus
Control Lines
DS39974A-page 201