PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 148

• Manufacturer Part Number: PIC18LF27J13T-I/SO
• Description: 28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J13T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F47J13 FAMILY
TABLE 10-5:
DS39974A-page 148
RB4/CCP4/
PMA1/KBI0/
SCL2
RB5/CCP5/
PMA0/KBI1/
SDA2
RB6/CCP6/
KBI2/PGC/RP9
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
(4)
(4)
Pin
2:
3:
4:
/RP7
/RP8
input/output; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option)
Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting
the appropriate bits in the ANCON1 register.
All other pin functions are disabled when ICSP™ or ICD is enabled.
Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
Only on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13).
PORTB I/O SUMMARY (CONTINUED)
Function
SDA2(4)
CCP4
CCP5
PMA0
CCP6
SCL2
PMA1
KBI0
KBI1
KBI2
PGC
RB4
RP7
RB5
RP8
RB6
RP9
(4)
(3)
(3)
(3)
(3)
Setting
TRIS
0
1
1
0
x
1
1
1
0
0
1
1
0
x
1
1
1
0
0
1
1
0
1
x
1
0
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST/TTL/
ST/TTL/
SMBus
SMBus
I
I
Type
2
2
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
TTL
DIG
I/O
ST
C™/
ST
ST
C™/
ST
ST
ST
ST
Preliminary
LATB<4> data output; not affected by an analog input.
PORTB<4> data input; weak pull-up when the RBPU bit is
cleared. Disabled when an analog input is enabled.
Capture input.
Compare/PWM output.
Parallel Master Port address.
Interrupt-on-change pin.
I
Remappable Peripheral Pin 7 input.
Remappable Peripheral Pin 7 output.
LATB<5> data output.
PORTB<5> data input; weak pull-up when the RBPU bit is
cleared.
Capture input.
Compare/PWM output.
Parallel Master Port address.
Interrupt-on-change pin.
I
Remappable Peripheral Pin 8 input.
Remappable Peripheral Pin 8 output.
LATB<6> data output.
PORTB<6> data input; weak pull-up when the RBPU bit is
cleared.
Capture input.
Compare/PWM output.
Interrupt-on-change pin.
Serial execution (ICSP™) clock input for ICSP and ICD
operation.
Remappable Peripheral Pin 9 input.
Remappable Peripheral Pin 9 output.
2
2
C clock input (MSSP2 module).
C data input (MSSP2 module).
(2)
Description
 2010 Microchip Technology Inc.
(1)