PIC18LF27J13T-I/SO Microchip Technology, PIC18LF27J13T-I/SO Datasheet - Page 528

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PIC18LF27J13T-I/SO

Manufacturer Part Number
PIC18LF27J13T-I/SO
Description
28-pin, GP, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SOIC .300in T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets

Specifications of PIC18LF27J13T-I/SO

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F47J13 FAMILY
TABLE 30-32: 10-BIT A/D CONVERSION REQUIREMENTS
TABLE 30-33: 12-BIT A/D CONVERSION REQUIREMENTS
DS39974A-page 528
130
131
132
135
137
Note 1:
130
131
132
135
137
Note 1:
Param
Param
No.
No.
2:
3:
4:
2:
3:
4:
T
T
T
T
T
T
T
T
T
T
Symbol
Symbol
AD
CNV
ACQ
SWC
AD
CNV
ACQ
SWC
DIS
DIS
The time of the A/D clock period is dependent on the device frequency and the T
ADRES registers may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
The time of the A/D clock period is dependent on the device frequency and the T
ADRES registers may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
A/D Clock Period
Conversion Time
(not including acquisition time)
Acquisition Time
Switching Time from Convert  Sample
Discharge Time
A/D Clock Period
Conversion Time
(not including acquisition time)
Acquisition Time
Switching Time from Convert  Sample
Discharge Time
Characteristic
Characteristic
DD
DD
(3)
(3)
to V
to V
SS
SS
or V
or V
SS
SS
(2)
(2)
Preliminary
to V
to V
DD
DD
). The source impedance (R
). The source impedance (R
CY
CY
cycle.
cycle.
Min
Min
0.7
1.4
0.2
0.8
1.4
0.2
13
11
(Note 4)
(Note 4)
25.0
12.5
Max
Max
12
14
(1)
(1)
Units
Units
T
T
s
s
s
s
s
s
AD
AD
S
S
) on the input channels is 50W.
) on the input channels is 50.
 2010 Microchip Technology Inc.
T
-40C to +85C
T
OSC
OSC
AD
AD
based, V
based, V
clock divider.
clock divider.
Conditions
Conditions
REF
REF
 3.0V
 3.0V

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