NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 75

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NSK70721PE.C2

Manufacturer Part Number
NSK70721PE.C2
Description
Manufacturer
Intel
Datasheet

Specifications of NSK70721PE.C2

Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Lead Free Status / RoHS Status
Supplier Unconfirmed
Datasheet
BIT_CLK, TBIT_CLK, and RBIT_CLK pulse
width (high)
BIT_CLK and TBIT_CLK delay from the
MSTR_CLK
QUAT_CLK and TQUAT_CLK delay from the
BIT_CLK and TBIT_CLK respectively
Transition time on any digital output
Transition time on any digital input
TFP setup time to BIT_CLK rising edge
TDATA setup time to BIT_CLK rising edge in
framed mode 6 and 7. TDATA setup time to
BIT_CLK and TBIT_CLK falling edge in
Transparent and Independent modes 0,1,2,4,
and 5.
TFP hold time from BIT_CLK rising edge
TDATA hold time to BIT_CLK rising edge in
framed mode 6 and 7. TDATA setup time to
BIT_CLK and TBIT_CLK falling edge in
Transparent and Independent modes 0,1,2,4,
and 5.
RDATA delay from BIT_CLK falling edge in
framed mode 6 and 7. RDATA delay from
BIT_CLK and RBIT_CLK rising edge in
Transparent and Independent modes 0,1,2,4,
and 5.
RFP delay from BIT_CLK falling edge
RDATA_ST delay from BIT_CLK falling edge
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. SLAVE_CLK must meet this tolerance about a frequency of 16 times the BIT_CLK frequency.
3. Measured with 15 pF load.
272 kbps
400 kbps
528 kbps
784 kbps
1168 kbps
Table 42. EMDP Data Interface Timing Specifications (Continued)
3
Parameter
3
Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721
Symbol
Tdasub
Tmbdly
Trdbdly
Tdahlb
Trfbdly
Tstbdly
Tbqdly
Ttfsub
Tbpw
Ttfhlb
Tto
Tti
Min
50
50
50
50
1.840
1.250
0.947
0.638
0.428
Typ
5
1
Max
50
25
10
25
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
75

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