NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 24

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set
3.1.5.4
24
MDSL Frame
Figure 7. MDSL Frame (4,702 bits per frame example)
Note: The EMDP frame sync word format and frame length are fully compatible with those defined for
784 and 1,168 kbps HDSL applications in the ITU G.991.1, ANSI Committee T1E1.4-TR28
(T1E1.4/96-006), and ETSI ETR-152 standards. The EMDP is fully transparent to all data except
the frame sync word. It does not provide other framing functions defined for HDSL.
Each frame contains either a 4,688 or 6,992 payload data bits. There are no restrictions on the data
patterns which can be transmitted in the payload data. The application synchronizes data to the
EMDP framing by generating a pulse on the transmit frame pulse input, TFP. The transmitter sends
the FSW in the first 14 bits following the rising edge of TFP. Application data is not transmitted or
buffered during the transmission of the FSW.
The EMDP receiver detects the incoming FSW and provides a blanking signal (RDATA_ST) at its
output to indicate that payload data is not present during the FSW. The RDATA_ST signal can also
be used to gate the receiver clock signal (BIT_CLK) so that clock transitions are present only when
payload data is available.
Bit Stuffing
Some applications require that data be transported at a rate which is externally controlled and
varies slightly from a nominal payload data rate. The EMDP framed mode allows the application to
modify the payload data rate slightly without changing the line rate so that each of the payload bits
contains a valid data bit. To operate in this mode, the EMDP uses a mechanism known as bit
stuffing. By properly choosing the line rate of the MDSL system and using the stuffing mechanism,
the application can transmit data at slightly different rates in both directions simultaneously while
using a common, fixed MDSL line rate.
When stuffing is employed, the application inserts an additional four bits not carrying payload data
in the data stream between the end of the 4,688 (or 6,992) payload bits and the beginning of the
next FSW as shown in
periods from its normal position. The EMDP receiver detects this four bit change in the location of
the FSW and adjusts its payload data strobe indicator (RDATA_ST) to indicate that the four
additional bits do not contain payload data and should be suppressed along with the FSW which
follows them. This mode of operation is frequently used in the transport of T1 or E1 signals where
the upstream and downstream data rates are not the same and are not exactly at the nominal rate.
1
•
Provides an MDSL frame position indicator that may be used in time-division-multiplexed
systems to relate time slots in the MDSL frame to those in an application frame (See Note
above).
0
1
0
1
Frame Sync Word
0
Figure
0
0
8. This is accomplished by delaying the TFP pulse by four BIT_CLK
0
0
1
0
0
0 b15 b16 b17 b18
Transparent Payload Data
b19
. . .
b4701 b4702
Datasheet