NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 62

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set
4.0
4.1
4.1.1
4.1.2
62
Application Information
PCB Layout
The following are general considerations for PCB layout using the EMDP chip set:
Digital Section
Analog Section
The analog section of the PCB consists of the following subsections:
1. IAFE and power supply decoupling capacitors.
2. Bias Current Generator.
3. Voltage Controlled Crystal Oscillator.
4. Line Interface Circuit.
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•
•
•
•
•
•
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Refer to
Use a four-layer or more PCB layout, with embedded power and ground planes. Bring the
digital power and ground planes over to include pins 1-6 and 24-28 of the IAF.
Break up the power and ground planes into the following regions. Tie these regions together at
the common point where power connects to the circuit:
Use larger “feed through” (via) and tracks for connecting the power and ground planes to the
power and ground pins of the ICs than for signal connections. Place the decoupling capacitors
right at the feed-through power/ground plane ties, or on the tracks to the IC power/ground pins
as close to the pins as possible.
On the User Interface Connector, route digital signals to avoid proximity to the TIP, RING,
and CT lines.
Provide at least 100 µF or more of bulk power supply decoupling at the point where power is
connected to the Data Pump circuit.
Keep all digital traces separated from the analog region of the Data Pump layout.
Provide high frequency decoupling capacitors (0.01 µF ceramic or monolithic) around the
EDSP as shown in
— Digital Region
— Analog Region
— VCXO subregion
— IAFE, Line I/F, and IBIAS subregion
— Route digital signals AD0, AD1, SRCTL_FS, SER_CTL, TSGN, TMAG, TX_CLK, and
— Route the following signal pairs as adjacent traces but keep the pairs separated from each
AGC_SET on the solder side of the PCB, and route all analog signals on the component
side as much as possible.
other as much as possible:
Figure 25
&
Figure 26
Figure
26, and
and
Figure
Table
27.
29.
Datasheet