NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 18

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set
3.1.1.3
3.1.2
18
Table 3.
the line code its name (1Q).
pulse amplitudes to bit pairs. Note that one bit of the pair is used to set the sign (the sign bit), while
the second bit (the magnitude bit) controls the magnitude of the pulse. The pulse shape is
independent of sign and magnitude and is described in
2B1Q Pulse Coding Rule
IAFE Receiver
The IAFE receiver is a sophisticated sigma-delta A/D converter. It subtracts the differential signal
at the balance input (BTIP/BRING) from the received signal (RTIP/RRING). The output is
generated in two stages. The first stage of A/D converter generates AD0 at 32 times the symbol
rate. The second stage of the A/D converter samples the noise generated by the first stage and
provides the AD1 bit stream at 32 times the symbol rate.
Receiver gain is controlled by the EDSP via the AGC0-2 bits in the Serial Control (SER_CTL)
stream. The AGC_SET output from the IAFE is normally low. It goes high when the signal level in
the sigma-delta A/D converter approaches its clipping level thus signaling the EDSP to lower the
gain.
The VCO is part of a PLL locked to the received data. The VCO frequency is varied by changing
the capacitive load of an external crystal with the help of Tuning Diodes that are biased by the
VPLL output. The VPLL output is, in turn, controlled by the EDSP through PLL bits of SER_CTL.
Enhanced MDSL Digital Signal Processor
The Enhanced MDSL Digital Signal Processor (EDSP) incorporates the following digital
functions:
A simple, parallel 8-bit microprocessor interface on the EDSP provides high-speed access to status,
control and filter coefficient words. The microprocessor interface provides bit flags for signal
presence, synchronization, activation completion. Single-byte words representing receive signal
level and the noise margin of the transceiver are also available on the microprocessor interface.
One control bit allows the user to start the Data Pump activation sequence. The EDSP controls the
complete activation/start-up sequence.
•
•
•
•
•
Sign
activation/start-up control, mode selection and the microprocessor interface
adaptive Echo-Cancelling (EC)
adaptive Decision Feedback Equalization (DFE), and Feed Forward Equalizer (FFE) using the
receive quat stream and the internal error signal
fixed and adaptive digital-filtering functions
bit-rate transmit and receive signal-processing including optional scrambling and
descrambling
Bit
1
1
0
0
Magnitude
Bit
0
1
1
0
Table 3
shows the encoding scheme used in the 2B1Q system to assign
Output Symbol
(quat)
+3
+1
-1
-3
Figure
28.
Datasheet