NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 13

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

(Independent
(Transparent
Datasheet
1. This input is a Schmidt Triggered circuit and includes an internal pull-up device.
2. This input is a Schmidt Triggered circuit and includes an internal pull-down device.
3. This input includes an internal pull-up device.
4. This input includes an internal pull-down device.
5. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output;
(Framed
Data I/F
Data I/F
Data I/F
Modes)
Modes)
Modes)
AI/O = Analog Input/Output; S = Supply.
Group
Table 2. EDSP Pin Assignments/Signal Descriptions (Continued)
Pin #
10
12
17
10
12
17
10
12
17
11
11
11
7
8
7
8
7
8
RQUAT_CLK
TQUAT_CLK
QUAT_CLK
RDATA_ST
RBIT_CLK
TBIT_CLK
UNUSED
UNUSED
BIT_CLK
BIT_CLK
Symbol
RDATA
RDATA
RDATA
TDATA
TDATA
TDATA
RFP
TFP
Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721
I/O
DO
DO
DO
DI
DO
DO
DO
DO
DO
DI
DO
DO
DO
DO
DO
DI
DI
DO
1
1
1
1
5
This pin is unused in Transparent Mode.
Receive Data. When ACTIVE is low, the received data is output on RDATA.
RDATA is high when ACTIVE is high. RDATA is aligned with the rising edge of
the BIT_CLK.
This pin is unused in Transparent Mode.
Transmit Data. When ACTIVE is low, the Data Pump samples TDATA on every
falling edge of BIT_CLK. In Transparent mode the user may either send the data
and allow the Data Pump to scramble the data or disable the scrambler and
independently control the sign and magnitude bits.
Quat Clock. One QUAT_CLK cycle occurs for each baud transmitted. The same
clock is used for both transmit and receive data.
Bit Clock. One BIT_CLK cycle occurs for each data bit. The same clock is used
for both transmit and receive data.
Receive Quat Clock. Baud rate clock aligned with received data.
Receive Data. When ACTIVE is low, the received data is output on RDATA.
RDATA is high when ACTIVE is high. RDATA is aligned with the rising edge of
the BIT_CLK.
Receive Data Clock. One RBIT_CLK cycle occurs for each received data bit.
Transmit Data. When ACTIVE is low, the Data Pump samples TDATA on every
falling edge of TBIT_CLK. In Independent mode the user may either send the
data and allow the Data Pump to scramble the data or disable the scrambler and
independently control the sign and magnitude bits.
Transmit Quat Clock. Baud rate clock for alignment of transmit data.
Transmit Data Clock. One TBIT_CLK cycle occurs for each data bit
transmitted.
Receive Frame Pulse. Low for one BIT_CLK cycle during the last bit of the
current MDSL receive frame. RFP is valid only when ACTIVE is low.
Receive Data Output. When ACTIVE is low, the receive data including frame
sync and stuff bits are output on RDATA. RDATA is high when ACTIVE is high.
RDATA is aligned with the falling edge of Bit-CLK.
Receive Data Strobe. RDATA_ST goes high during receipt of stuffing and
framing bits.
Transmit Data. When ACTIVE is low, the Data Pump samples TDATA at the
rising edge of BIT_CLK, except during frame sync and stuff bits.
Transmit Frame Pulse. TFP must be low during the last BIT_CLK cycle of each
transmitted MDSL frame. If TFP is pulled low and is low again three BIT_CLK
cycles later, RDATA, RFP, RDATA_ST, BIT_CLK, and ACTIVE will tristate until
the TFP is set high again.
Bit Rate Clock. This clock is used to transfer data into and out of the EMDP.
Description
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