NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 59

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.3.2
3.3.3
Datasheet
272
400
528
784
1,168
Line Rate
Table 28. MIT Register Setting Example
(kbps)
Desired MIT (msec):
Loopbacks
The EMDP chip set provides analog and digital loopbacks for system diagnostic purposes. The
analog Front End Loopback (FELB) loops the transmitted analog signal back towards the digital
interface, while the digital Back End Loop Back (BELB) loops the signal back toward the DSL
loop.
In FELB the IAFE receiver input is disabled while the balance network input remains active. The
line driver output is normally coupled back into the balance input through external components,
looping the transmitted data (TDATA plus any framing signal) back into the receiver and
eventually back to RDATA. In FELB the Data Pump receiver activates with its own transmit data
and ignores any signal present at the IAFE receiver. Data is transmitted on the line during FELB.
The far end (Slave) Data Pump may activate in response to the signal transmitted from the unit
under test. FELB is available only at the Master Data Pump. FELB is initiated only from the
Inactive state by asserting the FELB and the ACTREQ signals.
BELB is a data loopback inside the EDSP. Data received by the IAFE is processed through the
EDSP and then retransmitted on the DSL loop. BELB is available in both Master and Slave mode
at any time the Data Pump is Active. In BELB, the received data and framing signals are supplied
to the transmitter which ignores the TDATA and TFP inputs. Receive Data is also available on
RDATA during BELB. BELB is initiated by asserting BELB control.
FELB and BELB Loopbacks.
TIP/RING Reversal
DSL systems are designed to have the tip and ring leads connected directly, tip at the Master
connected to tip at the Slave and ring at the Master connected to the ring at the Slave. In some
installations the connection may be reversed, with tip connected to ring and vice versa. If this
condition is not detected and corrected, the receiver will improperly sense the sign of the received
signal. The EDSP automatically detects and corrects this condition in framed mode by sensing the
polarity of the framing signal and performing appropriate corrections.
In Transparent and Independent modes the EDSP is unable to detect the condition of the
connection from the received signal since no framing signal is defined. The EDSP allows the
application to invert the sense of the received signal by setting bit 7 in the Interrupt Mask and Line
Reversal Register (WR2).
7.35
5.00
3.78
2.55
1.71
Period
( sec)
Baud
15
10
8
5
4
Increment value
(msec)
Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721
Table 9
MIT Register Setting which first exceeds the period indicated (decimal)
1
2
3
4
7
describes the use of this register.
25
3
4
6
9
14
50
4
7
9
14
21
75
Figure 24
6
9
12
19
28
100
shows both the
66
97
128
191
N/A
1000
59