NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 38

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set
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structure for three pair HDSL systems. Both framing modes provide bit stuffing capability so that
pleisiochronous data streams may be transported without error and with acceptable jitter and
wander. The scrambler is always enabled when either mode 6 or mode 7 is selected.
This section provides guidance for the use of the EMDP in the framed mode. Detailed information
on operation in those modes is contained in the MDSL data sheets for the standard MDSL chip set
(SK70720/70721).
The EMDP data interface provides for the transfer of binary data to and from the transceiver using
the 272 to 1,168 kHz clock, BIT_CLK, generated by Data Pump.
data interface timing for modes 6 and 7. Since the only difference between these modes is the
number of bits per frame, the convention used in this section will be to write appropriate bit
numbers consequently for modes 6 and 7, separated by a slash (for instance, 4702/7006).
In the transmit direction, payload data is sampled from TDATA during bits b15-b4702/7006 of
each frame. Frame sync word bits (b1-b14) are internally generated in the EDSP. The state of
TDATA during b1-b14 is ignored. For fixed line rate applications an external counter must drive
the TFP input low for one complete BIT_CLK cycle. This signal on TFP establishes the start of an
MDSL frame - bit 1 of the frame begins immediately after the end of this signal on TFP. The
external data source must suppress data for 14 bit periods during the internally generated frame
synchronization word, bits 1-15. In variable line rate applications, bit stuffing logic adjusts the time
between TFP pulses to match the average line rate of the Data Pump and the data rate of the
external source. In both the cases - fixed and variable line rate, the TFP signal should be valid prior
to an activation request to the Master Data Pump. A valid TFP signal should be generated after
power-up, before or immediately after LOS goes low for the Slave Data Pump. During
initialization and anytime thereafter TFP must not be held low for more than 2 BIT_CLK cycles or
the data interface output signals will be disabled. If the TFP signal is inactive (always high or
unconnected) when activation starts, the Data Pump may activate but will inject synchronization
bits in every frame and stuff bits into every other frame. Since the Data Pump will not be
synchronized to the data source these internally generated bits will overwrite payload data. If the
position of TFP changes, the Data Pump will immediately reset the transmit frame alignment,
typically causing a temporary loss of frame alignment at the other end.
In the receive direction, the binary data output on RDATA contains the 14-bit frame
synchronization word (b1-b14), the transparent payload data (b15-b4702/7006) and optional stuff
bits (b4703-b4706/b7007-b7010). The data strobe signal RDATA_ST is high during the frame
synchronization word and stuff bits and low during payload data. RDATA_ST can be used to create
a gapped receive payload data clock by suppressing BIT_CLK cycles when RDATA_ST is high.
RFP is the receive frame synchronization output that goes low during the first bit of every MDSL
frame. In variable data rate applications the original data timing can be recovered from RFP using a
PLL.
During the activation process, no data are transmitted until the Noise Margin is greater than -5 dB
and the frame synchronization word has been detected in 6 consecutive frames. The output data
line, RDATA, is held high until ACTIVE goes low to indicate link activation has been completed.
•
Data Interface Timing
Figure 14
and
Figure 15
Datasheet
show the