PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 75

• Manufacturer Part Number: PSB50505EV13GXT
• Manufacturer: Lantiq

Specifications of PSB50505EV13GXT

• Lead Free Status / RoHS Status: Supplier Unconfirmed

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Operational Description
SRTS Invalid Value Processed Counter (“sriN”, see
Chapter
7.63) is incremented. In
case the number of out of window conditions during 16 SRTS periods exceeds the value
given by field “tr_srts” of register “treshN”, an out of lock message, indicated with bit “ols”
of register “oolN” is generated. During start-up of the RTS Receive FIFO, PLL-SRTS is
free running and bit “frr” of register “statN” is set.
4.5.11.2 PLL-FILTER
The PLL “PLL-FILTER” has a very low cut off frequency and a tuning range of ±240 ppm.
It reduces jitter which is generated in, or passed through PLL-SRTS. Although PLL-
FILTER is placed behind PLL-ACM, it has little or no functionality in case of ACM, as
PLL-ACM has a lower cut off frequency.
If more out of lock detections during 16 SRTS periods are detected than defined with
“tr_filt” in “tresh”, an out of lock message, indicated by bit “olf” of register “oolN”, is
generated.
4.5.11.3 PLL-ACM
The PLL-ACM is a control system with feedback of 2nd order. Its phase is adjusted
according to the filling level of the Reassembly Buffer.
The average buffer filling level as defined in bits “avb” in the Average Buffer Filling
Register (“avbN”, see
Chapter
7.52) is subtracted from the current buffer filling level.
The result is amplified in order to adjust the cut off frequency and to define the system’s
damping (number of bytes, needed to drive the DCO over its tuning range. The loop gain
is programmed in the ACM Shift Factor Register (asfN, see
Chapter
7.53). Although
adjustable, the PLL-cut-off frequency is generally less than 1 Hz. In conjunction with a
low pass filter, CDV is very small.
The behavior of the PLL is characterized by rise time and lock in time. The rise time is
the time when the clock output enters the predefined tuning range for the first time. The
lock in time is defined as the time after which the clock stays within the accepted
deviation.
Data Sheet
75
2003-01-20