PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 278

• Manufacturer Part Number: PSB50505EV13GXT
• Manufacturer: Lantiq

Specifications of PSB50505EV13GXT

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12.2
This sub chapter contains a short description of the SRTS method, as defined in [12] and
[31].
The SRTS algorithm is used to measure the frequency deviation of a data stream which
is packetized in ATM cells. This frequency is coded in 4 bits and sent to the receiver. At
the receiver, the correct frequency is regenerated.
The 4 RTS bits are spread over 8 ATM cells. These 8 ATM cells contain 8 x 47 byte x 8
bit/byte = 3008 bits of data. In case of an E1 line, the data arrives with 2.048 Mbit/s, thus
after 3008 bit / 2.048 Mbit/s = 1,46875 ms a complete RTS value is received. The
frequency of generated RTS values is 681 Hz.
The RTS value is calculated in the following way:
In N = 3008 cycles of Fdata, we have Mq cycles of the reduced network clock. The
reduced network clock Fnx has to fulfil the following equation: 1 <= Fnx / Fdata < 2. This
defines the value of x in the equation: Fnx = 8 kHz X 19440 / 2^x. For a full E1 line Fdata
= 2.048 MHz, x = 6 and Fnx = 2.43 MHz. The maximum input frequency deviation of 200
ppm (E1 lines: less than 50 ppm) of the data clock translates in a deviation from Mq. At
the receiving side, the same network clock is available and the numbers N and x are
known. As a result, the nominal value Mnom of Mq is known, and only the deviation from
Mnom has to be transmitted. The number of bits to transmit the deviation (p = 4) has to
be sufficient for the maximum frequency deviation.
Figure 76
Data Sheet
Synchronous Residual Time Stamp SRTS
f
f
nx
s
The Concept of SRTS (Fig. 5/I.363.1)
N cycles T seconds
M
q
278
PXB 4219E, PXB 4220E, PXB 4221E
M
min
tolerance
y
M
nom
2
p
y
M
T1817630-92
max
IWE8, V3.4
t
t
Appendix
2003-01-20