PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 60

• Manufacturer Part Number: PSB50505EV13GXT
• Manufacturer: Lantiq

Specifications of PSB50505EV13GXT

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The bit “sdt_par” in the “AAL Transmit Reference Slot” allows to disable the verification
of the parity bit in the pointer field.
For multiframe based SDT the bit “sdt_mfs” in the “AAL Transmit Reference Slot” has to
be set.
4.4.1.6
An internal signalling buffer holds the CAS bits. In case of buffer underflow or pointer
mismatch the IWE8 provides downstream CAS conditioning and freezing according to
Bellcore TR-NWT-000170 [14].
The selection between both is done individually for each channel via Bit “cond_en” in the
“AAL Transmit Conditioning Slot” of RAM4. Values for conditioning can be selected via
the “cond_down_nibble” bits in the same register.
The spare and alarm indication bits of the first E1 frame can be programmed by setting
bits cas0portN in the registers “cas1” and “cas2”. The CAS information of idle timeslots
can be chosen by setting bits in the register “cas3”.
4.4.1.7
Upon cell loss detection, the sequence count algorithm will insert dummy cells into the
Reassembly Buffer to maintain bit count integrity. The maximum amount of
consecutively inserted cells is 6.
These dummy cells are physically inserted when reading the Reassembly Buffer. The
Reassembly Buffer itself contains only control field in front of the payload of the next
accepted cell, indicating the amount of dummy cells to be inserted.
Inserted dummy cells are not taken into account for the ACM Reassembly Buffer filling
level calculation. This means that the buffer filling level is incorrect as long as dummy
cells are physically inserted.
The data octet used for the dummy cells is the byte-pattern selected by the “starv_bpslct”
field of the “AAL transmit reference slot” of RAM3.
4.4.1.8
The purpose of the Reassembly Buffer is to compensate the Cell Delay Variation (CDV)
of the ATM network.
It is located in external RAM providing 512 byte of memory for each timeslot, totalling to
128 KB for 8 ports with 32 timeslots each. The buffer for each timeslot consists of 8
memory blocks with 64 octets:
Buffer size = 8 Ports x 32 Channels x 8 Blocks x 64 Octets
Data Sheet
CAS Conditioning and Freezing Downstream
Insertion of Dummy Cells at Cell Loss
Reassembly Buffer
60
PXB 4219E, PXB 4220E, PXB 4221E
Operational Description
IWE8, V3.4
2003-01-20
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