PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 154

• Manufacturer Part Number: PSB50505EV13GXT
• Manufacturer: Lantiq

Specifications of PSB50505EV13GXT

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7.2
Read/write Address 00008
Reset value: 0000
a_icrc_dwn
a_hec_algor HEC detection, correction
a_hec_
mode
a_sw_reset
a_ut_en
a_ur_en
Data Sheet
a_icrc_
dwn
15
7
a_dummy_rts[2:0]
ASIC Configuration Register (acfg)
a_hec_
algor
ICRC power down
Once the SRTS block is switched off, it can only be enabled by hardware
reset of the whole device.
0 =
1 =
0 =
1 =
Handling in case of faulty HEC
0 =
1 =
Software reset
Reset registers 0000
0 =
1 =
UTOPIA transmit enable
0 =
1 =
UTOPIA receive enable
0 =
1 =
H
Enabled
Disabled
HEC algorithm according to ITU-T
HEC algorithm according to ATM Forum
Standard mode:
Cell discard upon detection of uncorrectable HEC error
as defined in pcfN.p_cell_disc
Normal
Reset
Disabled
Enabled
Disabled
Enabled
a_hec_
mode
H
a_emg_bpslct[1:0]
a_sw_
reset
H
to 0031
154
PXB 4219E, PXB 4220E, PXB 4221E
a_ut_en
H
including this bit.
a_ur_en a_crv_en
a_ovf_
cnt_en
Register Description
a_ptr_
prty
IWE8, V3.4
2003-01-20
a_dummy
a_even_
_rts[3]
pck
8
0