PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 200

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PSB50505EV13GXT

Manufacturer Part Number
PSB50505EV13GXT
Description
Manufacturer
Lantiq
Datasheet

Specifications of PSB50505EV13GXT

Lead Free Status / RoHS Status
Supplier Unconfirmed
7.44
Read only Address 00101
Reset value: 0000
irsN
crifo
scri
per
Bits are reset after reading the corresponding registers.
Data Sheet
irs4
15
7
Interrupt Source Register (irs)
irs3
IRS register of port N
These bits indicate if a bit is set in irsN
0 =
1 =
Clock recovery interface FIFO overflow
This bit indicates if a bit is set in crifo
0 =
1 =
Synchronization errors at the internal clock recovery interface
This bit indicates if a bit is set in scri
0 =
1 =
Parity errors at the clock recovery interface.
This bit indicates if a bit is set in per
0 =
1 =
H
False
True
False
True
False
True
False
True
Not used
irs2
H
irs1
200
PXB 4219E, PXB 4220E, PXB 4221E
irs0
crifo
irs7
Register Description
irs6
scri
IWE8, V3.4
2003-01-20
irs5
per
8
0

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