PSB50505EV13GXT Lantiq, PSB50505EV13GXT Datasheet - Page 32
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PSB50505EV13GXT
Manufacturer Part Number
PSB50505EV13GXT
Description
Manufacturer
Lantiq
Datasheet
1.PSB50505EV13GXT.pdf
(290 pages)
Specifications of PSB50505EV13GXT
Lead Free Status / RoHS Status
Supplier Unconfirmed
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Table 7
Pin No.
W9
Y14
2.2.8
Table 8
Pin No.
W1
U3
L2
L3
V2
Data Sheet
Miscellaneous
Test Interface (cont’d)
Miscellaneous
Symbol
Symbol
UTTR
OUTTR
E1/T1
EC
CLOCK
RESET
CLK52
Input (I)
Output (O)
I
PUA
I
Input (I)
Output (O)
I
PUA
I
PUA
I
I
PDA
I
Function
Utopia TRI-STATE
0 = tristate all Utopia outputs
1 = normal operation
Output TRI-STATE
0 = tristate all outputs and disable all pull-up
and pull-down resistors
1 = normal operation
Function
E1 or T1 Mode Select
0 = T1 mode
1 = E1 mode
Echo Canceller Mode Select
0 = echo canceller mode
1 = standard mode
Master Clock
Used to clock the core of the device
Master Hardware Reset
Asynchronous reset of all flip-flops
51.84 MHz SRTS Reference Clock
external reference clock for SRTS. If SRTS
mode is not used, it can be connected to V
32
PXB 4219E, PXB 4220E, PXB 4221E
Pin Descriptions
IWE8, V3.4
2003-01-20
SS
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