MT9P401I12STC Aptina LLC, MT9P401I12STC Datasheet - Page 28

• Manufacturer Part Number: MT9P401I12STC
• Description: SENSOR IMAGE CMOS 5MP 48LCC
• Manufacturer: Aptina LLC
• Type: CMOS Imagingr
• Series: DigitalClarity®r

Specifications of MT9P401I12STC

• Pixel Size: 2.2µm x 2.2µm
• Active Pixel Array: 2592H x 1944V
• Frames Per Second: 60
• Voltage - Supply: 2.6 V ~ 3.1 V
• Package / Case: 48-iLCC
• Sensor Image Color Type: Monochrome
• Sensor Image Size: 2592x1944Pixels
• Operating Supply Voltage (typ): 1.8/2.8V
• Operating Supply Voltage (max): 3.1V
• Operating Temp Range: -30C to 70C
• Package Type: ILCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1263; MT9P401I12STC; Q3412742

Table 13:
PDF: 09005aef82acb06f/Source: 09005aef81a4a477
MT9P401_DS_2 - Rev. B 9/07 EN
R0x00D
R0x010
R0x011
R0x012
Reg. #
R13:0
R16:0
R17:0
R18:0
Setting this bit will put the sensor into reset mode, which will set the sensor to its default power-up state and
cause it to halt. Clearing this bit will resume normal operation. This is equivalent to pulling RESET_BAR LOW,
except that the two-wire serial interface remains functional.
14:13
15:13
15:0
15:0
15:0
15:0
Bits
12:9
15:8
12:8
7:4
3:2
7:6
5:0
7:5
4:0
Register Description (continued)
15
8
1
0
Default
0x0000
0x0050
0x6404
0x0000
0x0000
0x0000
0x0000
0x0005
0x0000
0x0000
0x0064
0x0004
0x0000
0x0000
X
X
X
X
X
Name
Reset (RW)
PLL Control (RW)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Use PLL
When set, use the PLL output as the system clock. When clear, use EXTCLK as the system
clock.
Power PLL
When set, the PLL is powered. When clear, it is not powered.
PLL Config 1 (RW)
PLL m Factor
PLL output frequency multiplier.
Legal values: [16, 255].
Reserved
PLL n Divider
PLL output frequency divider minus 1.
Legal values: [0, 63].
PLL Config 2 (RW)
Reserved
Reserved
Reserved
PLL p1 Divider
PLL system clock divider minus 1. Use odd numbers. If this is set to an even number, the
system clock duty cycle will not be 50:50. In this case, set all bits in R101 or slow down
EXTCLK.
Legal values: [0, 127].
Micron Confidential and Proprietary
MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Registers