MT9P401I12STC Aptina LLC, MT9P401I12STC Datasheet - Page 17

• Manufacturer Part Number: MT9P401I12STC
• Description: SENSOR IMAGE CMOS 5MP 48LCC
• Manufacturer: Aptina LLC
• Type: CMOS Imagingr
• Series: DigitalClarity®r

Specifications of MT9P401I12STC

• Pixel Size: 2.2µm x 2.2µm
• Active Pixel Array: 2592H x 1944V
• Frames Per Second: 60
• Voltage - Supply: 2.6 V ~ 3.1 V
• Package / Case: 48-iLCC
• Sensor Image Color Type: Monochrome
• Sensor Image Size: 2592x1944Pixels
• Operating Supply Voltage (typ): 1.8/2.8V
• Operating Supply Voltage (max): 3.1V
• Operating Temp Range: -30C to 70C
• Package Type: ILCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1263; MT9P401I12STC; Q3412742

Serial Bus Description
Protocol
Sequence
Bus Idle State
Start Bit
PDF: 09005aef82acb06f/Source: 09005aef81a4a477
MT9P401_DS_2 - Rev. B 9/07 EN
1. a start bit
2. the slave device 8-bit address
3. an (a no) acknowledge bit
4. an 8-bit message
5. a stop bit
Registers are written to and read from the MT9P401 through the two-wire serial inter-
face bus. The MT9P401 is a serial interface slave and is controlled by the serial clock
(SCLK), which is driven by the serial interface master. Data is transferred into and out of
the MT9P401 through the serial data (S
off-chip by a 1.5kΩ resistor. Either the slave or master device can pull the S
LOW—the serial interface protocol determines which device is allowed to pull the S
line down at any given time.
The two-wire serial defines several different transmission codes, as follows:
A typical READ or WRITE sequence begins by the master sending a start bit. After the
start bit, the master sends the slave device's 8-bit address. The last bit of the address
determines if the request is a READ or a WRITE, where a “0” indicates a WRITE and a “1”
indicates a READ. The slave device acknowledges its address by sending an acknowledge
bit back to the master.
If the request is a WRITE, the master then transfers the 8-bit register address to which a
WRITE should take place. The slave sends an acknowledge bit to indicate that the
register address has been received. The master then transfers the data 8 bits at a time,
with the slave sending an acknowledge bit after each 8 bits. The MT9P401 uses 16-bit
data for its internal registers, thus requiring two 8-bit transfers to write to one register.
After 16 bits are transferred, the register address is automatically incremented, so that
the next 16 bits are written to the next register address. The master stops writing by
sending a start or stop bit.
A typical READ sequence is executed as follows. First the master sends the write-mode
slave address and 8-bit register address, just as in the WRITE request. The master then
sends a start bit and the read-mode slave address. The master then clocks out the
register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit
transfer. The register address is automatically-incremented after every 16 bits is trans-
ferred. The data transfer is stopped when the master sends a no-acknowledge bit.
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-
ated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line
is HIGH.
Micron Confidential and Proprietary
MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DATA
) line. The S
DATA
Serial Bus Description
line is pulled up to V
©2007 Micron Technology, Inc. All rights reserved.
DATA
line
DD
DATA
_IO