ADUC7126BSTZ126-RL Analog Devices Inc, ADUC7126BSTZ126-RL Datasheet - Page 90

• Manufacturer Part Number: ADUC7126BSTZ126-RL
• Description: ARM7 With 12-Bit ADC & DACs, 128kB Flash
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7126BSTZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 126KB (126K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7124/ADuC7126
Bit
[7:6]
[5:4]
[3:2]
[1:0]
IRQCLRE Register
Name:
Address:
Default Value:
Access:
Table 139. IRQCLRE MMR Bit Descriptions
Bit
[31:25]
24
23
22
21
20
[19:18]
17
[16:0]
Value
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
Name
PLA1CLRI
IRQ3CLRI
IRQ2CLRI
PLA0CLRI
IRQ1CLRI
IRQ0CLRI
Name
IRQ2SRC[1:0]
PLA0SRC[1:0]
IRQ1SRC[1:0]
IRQ0SRC[1:0]
IRQCLRE
0xFFFF0038
0x00000000
Write only
Description
Reserved. These bits are reserved and should not be written to.
A 1 must be written to this bit in the PLA IRQ1 interrupt service routine to clear an edge-
triggered PLA IRQ1 interrupt.
A 1 must be written to this bit in the external IRQ3 interrupt service routine to clear an edge-
triggered IRQ3 interrupt.
A 1 must be written to this bit in the external IRQ2 interrupt service routine to clear an edge-
triggered IRQ2 interrupt.
A 1 must be written to this bit in the PLA IRQ0 interrupt service routine to clear an edge-
triggered PLA IRQ0 interrupt.
A 1 must be written to this bit in the external IRQ1 interrupt service routine to clear an edge-
triggered IRQ1 interrupt.
Reserved. These bits are reserved and should not be written to.
A 1 must be written to this bit in the external IRQ0 interrupt service routine to clear an edge
triggered IRQ0 interrupt.
Reserved. These bits are reserved and should not be written to.
Description
External IRQ2 triggers on falling edge.
External IRQ2 triggers on rising edge.
External IRQ2 triggers on low level.
External IRQ2 triggers on high level.
PLA IRQ0 triggers on falling edge.
PLA IRQ0 triggers on rising edge.
PLA IRQ0 triggers on low level.
PLA IRQ0 triggers on high level.
External IRQ1 triggers on falling edge.
External IRQ1 triggers on rising edge.
External IRQ1 triggers on low level.
External IRQ1 triggers on high level.
External IRQ0 triggers on falling edge.
External IRQ0 triggers on rising edge.
External IRQ0 triggers on low level.
External IRQ0 triggers on high level.
Rev. B | Page 90 of 104