ADUC7126BSTZ126-RL Analog Devices Inc, ADUC7126BSTZ126-RL Datasheet - Page 85

• Manufacturer Part Number: ADUC7126BSTZ126-RL
• Description: ARM7 With 12-Bit ADC & DACs, 128kB Flash
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7126BSTZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 126KB (126K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IRQEN Register
IRQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled to
create an IRQ exception. When a bit is set to 0, the correspond-
ing source request is disabled or masked, which does not create
an IRQ exception. The IRQEN register cannot be used to
disable an interrupt.
IRQEN Register
Name:
Address:
Default Value:
Access:
IRQCLR Register
IRQCLR is a write-only register that allows the IRQEN register
to clear to mask an interrupt source. Each bit that is set to 1
clears the corresponding bit in the IRQEN register without
affecting the remaining bits. The pair of registers, IRQEN and
IRQCLR, allow independent manipulation of the enable mask
without requiring an atomic read-modify-write.
This register should be used to disable an interrupt source only
during the following conditions:
•
•
This register should not be used to disable an IRQ source if that
IRQ source has an interrupt pending or may have an interrupt
pending.
IRQCLR Register
Name:
Address:
Default Value:
Access:
FAST INTERRUPT REQUEST (FIQ)
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface and provides the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Bit 31 to Bit 1 of FIQSTA are logically OR’ e d to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN clears, as a side effect, the same bit in IRQEN.
In the interrupt sources interrupt service routine.
When the peripheral is temporarily disabled by its own
control register.
IRQCLR
0xFFFF000C
0x00000000
Write only
IRQEN
0xFFFF0008
0x00000000
Read/write
Rev. B | Page 85 of 104
Likewise, a bit set to 1 in IRQEN clears, as a side effect, the
same bit in FIQEN. An interrupt source can be disabled in both
the IRQEN and FIQEN masks.
FIQSIG
FIQSIG reflects the status of the different FIQ sources. If a
peripheral generates an FIQ signal, the corresponding bit in
the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are
cleared when the interrupt in the particular peripheral is
cleared. All FIQ sources can be masked in the FIQEN MMR.
FIQSIG is read only.
FIQSIG Register
Name:
Address:
Default Value:
Access:
FIQEN
FIQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled to
create an FIQ exception. When a bit is set to 0, the correspond-
ing source request is disabled or masked, which does not create
an FIQ exception. The FIQEN register cannot be used to disable an
interrupt.
FIQEN Register
Name:
Address:
Default Value:
Access:
FIQCLR
FIQCLR is a write-only register that allows the FIQEN register
to clear to mask an interrupt source. Each bit that is set to 1
clears the corresponding bit in the FIQEN register without
affecting the remaining bits. The pair of registers, FIQEN and
FIQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
This register should be used to disable an interrupt source only
during the following conditions:
•
•
This register should not be used to disable an IRQ source if that
IRQ source has an interrupt pending or may have an interrupt
pending.
In the interrupt sources interrupt service routine.
The peripheral is temporarily disabled by its own control
register.
FIQEN
0xFFFF0108
0x00000000
Read/write
FIQSIG
0xFFFF0104
0x00000000
Read only
ADuC7124/ADuC7126