ADUC7126BSTZ126-RL Analog Devices Inc, ADUC7126BSTZ126-RL Datasheet - Page 67

• Manufacturer Part Number: ADUC7126BSTZ126-RL
• Description: ARM7 With 12-Bit ADC & DACs, 128kB Flash
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7126BSTZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 126KB (126K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Registers
The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPI Status Register
Name:
Address:
Default Value:
Access:
Function:
Table 100. SPISTA MMR Bit Descriptions
Bit
[15:12]
11
[10:8]
7
6
5
4
[3:1]
0
Name
SPIREX
SPIRXFSTA[2:0]
SPIFOF
SPIRXIRQ
SPITXIRQ
SPITXUF
SPITXFSTA[2:0]
SPIISTA
SPISTA
0xFFFF0A00
0x0000
Read only
This 32-bit MMR contains the status of the SPI interface in both master and slave modes.
Description
Reserved.
SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the
SPIMDE bits in SPICON
This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE.
SPI Rx FIFO status bits.
[000] = Rx FIFO is empty.
[001] = one valid byte in the FIFO.
[010] = two valid bytes in the FIFO.
[011] = three valid bytes in the FIFO.
[100] = four valid bytes in the FIFO.
SPI Rx FIFO overflow status bit.
Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt
except when SPIRFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI Rx IRQ status bit.
Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required
number of bytes has been received.
Cleared when the SPISTA register is read.
SPI Tx IRQ status bit.
Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number
of bytes has been transmitted.
Cleared when the SPISTA register is read.
SPI Tx FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt
except when SPITFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI Tx FIFO status bits.
[000] = Tx FIFO is empty.
[001] = one valid byte in the FIFO.
[010] = two valid bytes in the FIFO.
[011] = three valid bytes in the FIFO.
[100] = four valid bytes in the FIFO.
SPI interrupt status bit.
Set to 1 when an SPI-based interrupt occurs.
Cleared after reading SPISTA.
Rev. B | Page 67 of 104
ADuC7124/ADuC7126