ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 83

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

LIN DIAGNOSTIC
The ADuC7039 features a short-circuit protection on the
LIN pin. If a short-circuit condition is detected on the LIN
pin, HVSTA[0] is set. This generates a high voltage interrupt
if enabled in IRQEN[10]. This bit is cleared by re-enabling the
LIN driver using HVCFG[2]. It is possible to disable this feature
through HVCFG[1].
LIN COMMUNICATION
LIN uses frames for data communication. A frame consists of a
header, break, synch, PID issued by the master, and data bytes,
plus checksum generated by a slave as shown in Figure 32. In a
LIN communication, the PID dictates the behavior of the slave:
receive, transmit, or ignore.
Break
The LIN interface of the ADuC7039 automatically detects the
break and sets a flag in the LINSTA register after receiving a
valid break. The minimum length of the break symbol is 11
nominal slave clocks (at 20 kB). The maximum length of a
valid break symbol is programmable and can be configured in
the LINBK MMR. The LIN interface recognizes a valid break
at any time during a LIN communication and flags a collision
(Bit 4 of LINSTA) if the break occurred during an existing
communication.
Synch
The LIN interface automatically detects the synch byte and sets
the baud rate for the subsequent data of the current LIN frame.
This operation is transparent to the user.
PID
The LIN peripheral sees the PID as a data byte. It is available in
the LINDAT MMR. The software must decode the PID. After
reception of the PID stop bit, an interrupt is generated to read
the contents of the LINDAT register before the contents are
overwritten by the next data byte.
Data Bytes
Subsequent data bytes similarly set the interrupt bit to indicate
that a data byte has been received.
In transmit mode, up to 8 data bytes can be transmitted at a
time followed by a checksum.
Checksum
Checksums are automatically calculated as each byte is received
or transmitted with the inverted value being stored in the
LINCS MMR. By default, checksum calculation are per LIN 2.1
specifications, that is, with enhanced checksum calculations
for all frames except the diagnostic frames and reserved frames
where the classic checksum calculation is used. The hardware
automatically recognizes the PID and calculates the checksum
accordingly. There is no requirement for user code to write to
the LINCON register to change the checksum calculation.
Rev. B | Page 83 of 92
To operate in LIN 1.3 mode, user code LIN initialization
routine must set LINCON[7] to 1, to force the hardware in
classic checksum calculation. This register should not be
modified during LIN communication in receive mode.
LIN MMRS
The interface to the LIN block consists of 8 MMRs:
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LINCON is a 16-bit control register. This MMR is described
in Table 61. This register should not be accessed during
data reception.
LINDAT is an 8-bit user accessible data register. This
MMR is double-buffered: a shadow register is used to
receive and transmit while user code reads and writes
from/to LINDAT. The LINSTA MMR indicates the
status of the data.
LINSTA is a 16-bit status register. This MMR is described
in Table 62.
LINBR is a 19-bit baud rate register. The baud rate is
automatically set by the LIN peripheral and this register
should not be altered by user code. It indicates the number
of core clock ticks during an 8-bit transmission.
LINBK is a 19-bit break timer register controlling the
maximum length of a break symbol to be detected by the
LIN slave interface as valid. The default count is 5500 core
clock ticks. This represents the time taken for 11 bits to be
transmitted at 20 kHz.
LINCS is an 8-bit checksum register. It contains the
inverted result of the current checksum calculation. The
checksum calculation is performed on every byte that is
received or transmitted according to the setting of Bit 4
in LINCON MMR. In transmit mode, the user sets the
bit after the last data to transmit has been written in the
peripheral. The checksum is sent automatically. In receive
mode, the checksum is calculated on receiving each byte,
regardless if this byte is a data byte or the frame checksum.
For example, when receiving a frame with 4 data bytes, the
LINCS MMR contains the expected frame checksum once
the fourth data byte is received. LINCS should contain
0x00 after receiving a correct checksum.
LINLOW is a 19-bit counter clocked at 10 MHz to wake
up the LIN nodes on the bus. The LIN bus is forced low as
long as the LINLOW MMR is greater than 0. For example,
LINLOW = 0x234 generates an 11-bit break at 20 kB.
LINWU is a 19-bit counter clocked by the low power
oscillator. It is used in sleep mode to specify the length
of the low signal that wakes up the device via LIN. For
example, LINWU = 0x13 ignores any breaks of less than
150 μs, and the ADuC7039 remains asleep.
ADuC7039