ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 15

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

The remap command must be executed from the absolute
Flash/EE address, and not from the mirrored, remapped
segment of memory, because this may be replaced by SRAM. If
a remap operation is executed while operating code from
the mirrored location, prefetch/data aborts can occur, or the
user can observe abnormal program operation.
Any kind of reset logically remaps the Flash/EE memory to
the bottom of the memory array.
SYSMAP Register
Name:
Address:
Default Value:
Access:
Function:
Table 7. SYSMAP MMR Bit Designations
Bit
7 to 1
0
RESET
There are four kinds of reset: external reset, power-on-reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can also be written
by user code to initiate a software reset event. The bits in this
register can be cleared to 0 by writing to the RSTCLR MMR at
0xFFFF0234. The bit designations in RSTCLR mirror those of
RSTSTA. These registers can be used during a reset exception
service routine to identify the source of the reset. The implica-
tions of all four kinds of reset event are tabulated in Table 9.
Table 9. Device Reset Implications
RESET
POR
Watchdog
Software
External Pin
1
2
RAM is not valid in the case of a reset following LIN download.
The impact on RAM is dependent on the HVSTA[2] contents if LVF is enabled. When LVF is enabled using HVCFG[4], RAM has not been corrupted by the POR reset
mechanism if the LVF Status Bit HVSTA[2] is 1. See the Low Voltage Flag (LVF) section for more information.
Description
Reserved. These bits are reserved and should be written
as 0 by user code.
Remap bit.
This bit is set by the user to remap the SRAM to
0x00000000.
This bit is cleared automatically after reset to remap the
Flash/EE memory to 0x00000000.
Reset External
Pins to Default
State
Yes
Yes
Yes
Yes
Updated by the kernel
SYSMAP
0xFFFF0220
Read/write
This 8-bit register allows user code to remap
either RAM or Flash/EE space into the bottom
of the ARM memory space starting at Address
0x00000000.
Kernel
Executed
Yes
Yes
Yes
Yes
Reset All External
MMRs (Excluding
RSTSTA)
Yes
Yes
Yes
Yes
Rev. B | Page 15 of 92
Reset All HV
Indirect
Registers
Yes
Yes
Yes
Yes
Impact
RSTSTA Register
Name:
Address:
Default Value:
Access:
Function:
RSTCLR Register
Name:
Address:
Access:
Function:
Table 8. RSTSTA/RSTCLR MMR Bit Designations
Bit
7 to 4
3
2
1
0
1
clear this bit generates a software reset.
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
Peripherals
Reset
Yes
Yes
Yes
Yes
Description
Not used. These bits are not used and always read as 0.
External reset.
This bit is set by hardware when an external reset occurs.
This bit is cleared by setting the corresponding bit in RSTCLR.
Software reset.
This bit is set by user code to generate a software reset.
This bit is cleared by setting the corresponding bit in RSTCLR.
Watchdog timeout.
This bit is set by hardware when a watchdog timeout occurs.
This bit is cleared by setting the corresponding bit in RSTCLR.
Power-on reset.
This bit is set by hardware when a power-on-reset occurs.
This bit is cleared by setting the corresponding bit in RSTCLR.
RSTCLR
0xFFFF0234
Write only
This 8-bit write-only register clears the
corresponding bit in RSTSTA.
RSTSTA
N/A
Read/write
This 8-bit register indicates the source of the
last reset event and can also be written by user
code to initiate a software reset.
0xFFFF0230
Watchdog
Timer Reset
Yes
No
No
No
RAM
Valid
Yes/No
Yes
Yes
Yes
1
2
RSTSTA (Status
After Reset Event)
RSTSTA[0] = 1
RSTSTA[1] = 1
RSTSTA[2] = 1
RSTSTA[3] = 1
ADuC7039
1