ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 50

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ADUC7039BCP6Z-RL

Manufacturer Part Number
ADUC7039BCP6Z-RL
Description
Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet

Specifications of ADUC7039BCP6Z-RL

Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI
Peripherals
POR, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
32-LFCSP
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7039BCP6Z-RL
Manufacturer:
NS/国半
Quantity:
20 000
ADuC7039
PLLSTA Register
Name:
Address:
Default Value:
Access:
Function:
Table 37. PLLSTA MMR Bit Designations
Bit
7 to 2
1
0
PLLCON Prewrite Key PLLKEY0
Name:
Address:
Access:
Key:
Function:
PLLCON Postwrite Key PLLKEY1
Name:
Address:
Access:
Key:
Function:
PLLCON Register
Name:
Address:
Default Value:
Access:
Function:
PLLKEY0
0xFFFF0410
Write only
0x000000AA
PLLCON is a keyed register that requires a 32-bit key value to be written before and after PLLCON. PLLKEY0 is the
prewrite key.
PLLKEY1
0xFFFF0418
Write only
0x00000055
PLLCON is a keyed register that requires a 32-bit key value to be written before and after PLLCON. PLLKEY1 is the
postwrite key.
PLLCON
0xFFFF0414
0x00
Read/write
This 8-bit register allows user code to dynamically select the PLL source clock from two different oscillator sources.
Description
Reserved.
PLL lock status bit, read only.
This bit is set automatically when the PLL is locked and outputting 20.48 MHz.
This bit is cleared automatically when the PLL is not locked and outputting an f
PLL interrupt.
Set this bit if the PLL lock status bit signal goes low.
This bit is cleared by user code when writing 1 to this bit.
PLLSTA
0xFFFF0400
0xXX
Read only
This 8-bit register allows user code to monitor the lock state of the PLL.
Rev. B | Page 50 of 92
CORE
divide-by-8 clock source.

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