ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 82

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

ADuC7039
LIN (LOCAL INTERCONNECT NETWORK) INTERFACE
LIN PHYSICAL INTERFACE
The ADuC7039 features a high voltage physical interface
between the ARM7 MCU core and an external LIN bus. The
LIN interface operates as a slave only interface, operating from
1 kB to 20 kB and is compatible with the LIN 2.1 standard.
Frequencies below 1 kB are interpreted as 1 kB. The pull-up
resistor required for a slave node is on-chip, reducing the
need for external circuitry. Some external components are
recommended, on the LIN pin, for best performance for
EMC and fault protection (see Figure 33).
OSCILLATOR
LOW POWER
LIN INTERRUPT
IRQEN[5]
10MHz
INTERRUPT
LINDAT
MASK
LINCS
LINBK
LINBR
LOGIC
LIN
BREAK
13T
IRQEN[10]
DISABLE
OUTPUT
> = 14T
HV IRQ
RxD
TxD
BIT
BIT
SHORT-CIRCUIT
>1T
LIN MODE
HVCFG[0]
CONTROL
BPF
HVCFG[1]
BIT
STA S0
2T
Figure 31. LIN Physical Interface
BIT
Rev. B | Page 82 of 92
SYNC
Figure 32. LIN Frame
S1
INTERNAL
SHORT-CIRCUIT
TRIP REFERENCE
2T
INPUT
VOLTAGE
THRESHOLD
REFERENCE
8T
BIT
S2
BIT
S3
2T
BIT
S4
The LIN protocol is emulated using an IRQ/FIQ, dedicated
LIN timers, and the high voltage transceiver also incorporated
on chip as shown in Figure 31. The LIN is clocked from the
low power oscillator when the device is in sleep mode, and
from the 10 MHz core clock in normal mode.
The LIN transceiver is enabled via the 2-wire interface,
HVCFG[0]. The LIN protocol is controlled by 8 MMRs
described in the LIN MMRs section.
VDD
S5
INTERNAL
SHORT-CIRCUIT
SENSE RESISTOR
2T
PROTECTION
BIT
S6
VOLTAGE
S7 STO
OVER
IO_VSS
SCR
PROTECTED ID
EXTERNAL
LIN PIN
VDD
MASTER ECU
PROTECTION
DIODE
MASTER ECU
PULL-UP
C
LOAD