ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 58

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

ADuC7039
INTERRUPT SYSTEM
There are 10 interrupt sources on the ADuC7039 that are con-
trolled by the interrupt controller. Most interrupts are generated
from the on-chip peripherals such as the ADC and timers. The
ARM7TDMI-S CPU core only recognizes interrupts as one of
two types: a normal interrupt request (IRQ) and a fast interrupt
request (FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system is
managed through nine interrupt-related registers: four
dedicated to IRQ and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source.
The bits in each IRQ and FIQ register represent the same
interrupt source as described in Table 44.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
The interrupt generation to the ARM7TDMI-S core is shown
in Figure 22.
Consider the example of Timer0, which is configured to
generate a timeout every 5 ms. After the first 5 ms timeout,
FIQSIG/IRQSIG[2] is set and can only be cleared by writing
to T0CLRI. If Timer0 is not enabled in either IRQEN or
FIQEN, then FIQSTA/IRQSTA[2] is not set and an interrupt
does not occur. However, if Timer0 is enabled in either IRQEN
or FIQEN, then either FIQSTA/IRQSTA[2] is set or an interrupt
(either an FIQ or IRQ) occurs.
Tab
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12 to 31
le 44. IR
Low power oscillator calibration complete
Q/FIQ MMR
Description
All interrupts OR’ed
SWI
Timer0
Timer1 or wake-up timer
Timer2 or watchdog timer
LIN
Flash/EE interrupt
PLL lock
ADC
SPI
High voltage
Reserved
s Bit Designations
Rev. B | Page 58 of 92
Comments
Only available in the FIQ MMRs
Not used in IRQEN/CLR and FIQEN/CLR
Note that the IRQ a
only control interrupt recognition by the ARM core, not by the
peripherals. For example, if Timer2 is configured to generate an
IRQ via IRQEN, the IRQ interrupt bit is set (disabled) in the
CPSR, and the ADuC7039 is powered down. When an interrupt
occurs, the peripherals are woken, but the ARM core remains
powered down. This is equivalent to POWCON = 0x71. The
ARM core can only be powered up by a reset event if this occurs.
PLL LOCK
PLL LOCK
FLASH/EE
FLASH/EE
LIN H/W
LIN H/W
TIMER0
TIMER1
TIMER2
TIMER0
TIMER1
TIMER2
ADC
ADC
SPI
SPI
HV
HV
nd FIQ interrupt bit defini
Figure 22. Interrupt Structure
tions in the CPSR
IRQ
FIQ