ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 34

no-image

ADUC7039BCP6Z-RL

Manufacturer Part Number
ADUC7039BCP6Z-RL
Description
Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet

Specifications of ADUC7039BCP6Z-RL

Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI
Peripherals
POR, Temp Sensor, WDT
Number Of I /o
6
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
32-LFCSP
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free by exemption / RoHS compliant by exemption

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7039BCP6Z-RL
Manufacturer:
NS/国半
Quantity:
20 000
ADuC7039
ADC Interrupt Mask Register
Name:
Address:
Default Value:
Access:
Function:
ADC Mode Register
Name:
Address:
Default Value:
Access:
Function:
Table 28. ADCMDE MMR Bit Designations
Bit
7 to 6
5
4
3
2 to 0
Description
Not used. These bits are reserved for future functionality and should be written as 0 by user code.
ADC enable continuous interrupt.
This bit is set to 1 to enable ADCSTA[5].
This bit is set to 0 by default.
Reserved.
ADC power mode configuration.
0 = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance.
1 = ADC low power mode. If enabled, the ADC operates with reduced current consumption. In this mode, the gain is fixed to 512.
ADC operation mode configuration.
0, 0, 0 = ADC power-down mode. All ADC circuits are powered down.
0, 0, 1 = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts.
0, 1, 0 = ADC single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC enters idle mode when the
single shot conversion is complete. A single conversion takes two to three ADC clock cycles depending on the chop mode.
0, 1, 1 = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset.
1, 1, 0 = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC channels against
an external zero-scale voltage applied to the ADC input pins. The calibration is carried out at the user programmed ADC settings;
therefore, as with a normal, single ADC conversion, it takes the full ADC filter settling time before a fully settled calibration result is
ready. The results (offset coefficients) are available in the ADCxDAT MMR when ADCSTA[15] is set. User software should copy the
result of the conversion to the ADCxOF MMR.
1, 1, 1 = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC channels against an
external full-scale voltage applied to the ADC input pins. The results (gain coefficients) are available in the ADCxDAT MMR when
ADCSTA[15] is set. User software should copy the result of the conversion to the ADCxGN MMR.
Other = reserved.
ADCMDE
0xFFFF0508
0x00
Read/write
The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem.
ADCMSKI
0xFFFF0504
0x00
Read/write
This register allows the ADC interrupt sources to be individually enabled. The bit positions in this register are
the same as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to a 1, the respective interrupt
is enabled. By default, all bits are 0, meaning all ADC interrupt sources are disabled. Note that ADCMSKI[2:0]
should not be set if ADCMSKI[5] is set.
Rev. B | Page 34 of 92

Related parts for ADUC7039BCP6Z-RL