ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 52

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

ADuC7039
Table 39. POWCON MMR Bit Designations
Bit
11 to 9
8
7 to 6
5
4
3
2 to 0
Description
Reserved. These bits should be written as 0.
Precision oscillator enable.
This bit is set by the user to enable the precision oscillator.
This bit is cleared by the user to power down the precision oscillator.
Reserved. These bits should be written as 0.
PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active clock
source remain active.
This bit is set by default, and set by hardware on a wake-up event.
This bit is cleared to 0 to power down the PLL. The PLL should not be powered down if either the core or peripherals are
enabled: Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
Peripherals power-down. The peripherals that are powered down by this bit are as follows: SRAM, Flash/EE memory and
GPIO interfaces, and SPI port.
This bit is set by default, and/or by hardware, on a wake-up event. Wake-up timer (Timer2) can still be active if driven
from low power oscillator even if this bit is set.
This bit is cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled: Bit 3
and Bit 4 must be cleared simultaneously. LIN can still respond to wake-up events even if this bit is cleared.
Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command is
written to POWCON.
This bit is set by default, and set by hardware on a wake-up event.
This bit is cleared to power down the ARM core.
Core clock divider (CD) bits.
000 = 20.48 MHz, 48.83 ns.
001 = 10.24 MHz, 97.66 ns (this is the default setting at power-up).
010 = 5.12 MHz, 195.31 ns.
011 = 2.56 MHz, 390.63 ns.
100 = 1.28 MHz, 781.25 ns.
101 = 640 kHz, 1.56 μs.
110 = 320 kHz, 3.125 μs.
111 = 160 kHz, 6.25 μs.
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