IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 99

• Manufacturer Part Number: IPTR-C2H-NIOS
• Description: IP CORE Renewal Of IPT-C2H-NIOS
• Manufacturer: Altera

Specifications of IPTR-C2H-NIOS

• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: Nios II
• Features: ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Example 4–1. Vector Power Calculation
#pragma altera_accelerate connect_variable power_calculation/voltage to onchipRAM1
#pragma altera_accelerate connect_variable power_calculation/current to onchipRAM1
#pragma altera_accelerate connect_variable power_calculation/power to onchipRAM2
void power_calculation ( short * _ _restrict__ voltage,
{
}
Altera Corporation
November 2009
int i;
for(i = 0; i < length; i++)
{
}
*power++ = (*voltage++ * *current++) >> downscale;
short * _ _restrict_ _ current,
short * _ _restrict_ _ power,
short downscale,
int length)
Example 4–1
perform memory accesses. It also requires a multiplier and a barrel shifter
to perform the right shift operation. The pragma statements inform the
C2H Compiler that the input data is stored in a memory called
onchipRAM1 and the output data is to be stored in onchipRAM2. When
the C2H Compiler compiles this function, the Nios II IDE generates a
build report as shown in
Nios II C2H Compiler User Guide
requires Avalon-MM read and write master ports to
9.1
Figure
4–1.
Understanding the C2H View
4–5