IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 82

• Manufacturer Part Number: IPTR-C2H-NIOS
• Description: IP CORE Renewal Of IPT-C2H-NIOS
• Manufacturer: Altera

Specifications of IPTR-C2H-NIOS

• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: Nios II
• Features: ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Scheduling
Example 3–35. Loop Block
int mac(int *data_array, int *coef_array, int len)
{
}
3–42
Nios II C2H Compiler User Guide
int sum = 0;
do
{
} while (i++ < len);
return sum;
int x = *data_array++;
int c = *coef_array++;
int prod = c * x;
sum += prod;
Memory Transfers
Avalon-MM system interconnect fabric manages arbitration between
multiple Avalon-MM master ports that access a single slave port. A
master port might have to wait several clock cycles before beginning a
transfer due to arbitration. If a master port on an accelerator is being
forced to wait, the state machine for the accelerator stalls until the transfer
can proceed.
Loop Pipelining
The C2H Compiler structures the state machine for a loop so that
iterations of the loop are pipelined. In other words, consecutive iterations
of the loop can begin before prior iterations have completed.
Pipelining Loop Iterations
Figure 3–20
Example
3–35.
shows the dependency graph for the loop block in
9.1
Altera Corporation
November 2009