IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 100
IPTR-C2H-NIOS
Manufacturer Part Number
IPTR-C2H-NIOS
Description
IP CORE Renewal Of IPT-C2H-NIOS
Manufacturer
Altera
Datasheet
1.IPT-C2H-NIOS.pdf
(138 pages)
Specifications of IPTR-C2H-NIOS
Software Application
IP CORE, NIOS Processor And Functions
Core Architecture
Nios II
Features
ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
Core Sub-architecture
Cyclone
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Resources
Figure 4–1. Build Report - Resources
4–6
Nios II C2H Compiler User Guide
The resources section contains a subsection for each type of resource. The
report shows Avalon-MM master port resources in a different layout from
other operator resources due to the differences between the functionality.
Avalon-MM Master Port Resources
The C2H Compiler uses Avalon-MM master ports to implement
dereference operations (memory accesses). The resources section of the
C2H build report shows each Avalon-MM master port created by the C2H
Compiler. The C2H Compiler creates the optimal number of master ports
for the memory accesses it finds in the code. The C2H Compiler conserves
Avalon-MM resources by creating a single Avalon-MM master port to
access memory for multiple dereference operations if there is no
performance disadvantage. In
voltage and current reside in the same single-ported physical
9.1
Example
4–1, the data pointed to by
Altera Corporation
November 2009
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