IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 4

• Manufacturer Part Number: IPTR-C2H-NIOS
• Description: IP CORE Renewal Of IPT-C2H-NIOS
• Manufacturer: Altera

Specifications of IPTR-C2H-NIOS

• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: Nios II
• Features: ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Contents
Chapter 3. C-to-Hardware Mapping Reference
Chapter 4. Understanding the C2H View
Chapter 5. Accelerating Code Using the Nios II Software Build Tools Command Line
Chapter 6. Pragma Reference
iv
Nios II C2H Compiler User Guide
Next Steps ............................................................................................................................................. 2–16
One-to-One C-to-Hardware Mapping ................................................................................................ 3–1
Variable Declarations .......................................................................................................................... 3–13
Memory Accesses ................................................................................................................................ 3–15
Scheduling ............................................................................................................................................ 3–30
Resource Sharing ................................................................................................................................. 3–51
Introduction ............................................................................................................................................ 4–1
Overview ................................................................................................................................................. 4–1
Resources ................................................................................................................................................ 4–3
Performance .......................................................................................................................................... 4–10
Further Reading ................................................................................................................................... 4–19
Creating an Accelerator from the Command Line ........................................................................... 5–1
C2H Performance Metrics .................................................................................................................... 5–2
Introduction ............................................................................................................................................ 6–1
Arithmetic and Logical Operators ................................................................................................. 3–1
Assignments ...................................................................................................................................... 3–2
Iteration Statements ......................................................................................................................... 3–5
Selection Statements ......................................................................................................................... 3–6
Subfunction Calls ........................................................................................................................... 3–11
Macros and Preprocessing Directives ......................................................................................... 3–13
Local vs. Non-Local Variables ...................................................................................................... 3–13
Scalar Variables ............................................................................................................................... 3–14
Indirection Operator (Pointer Dereference) ............................................................................... 3–16
Avalon-MM Master Port Signal Generation .............................................................................. 3–20
Array Subscript Operator .............................................................................................................. 3–26
Structure and Union Operators .................................................................................................... 3–28
Scheduling Concepts for Hardware Accelerators ..................................................................... 3–30
Pointer Aliasing .............................................................................................................................. 3–32
Read Operations with Latency ..................................................................................................... 3–37
Stalling ............................................................................................................................................. 3–39
Loop Pipelining .............................................................................................................................. 3–42
Subfunction Pipelining .................................................................................................................. 3–49
Generation/Compilation Configurations ..................................................................................... 4–1
Avalon-MM Master Port Resources .............................................................................................. 4–6
Mathematical Operator Resources ................................................................................................. 4–8
Source Line Number ...................................................................................................................... 4–10
Loop Latency ................................................................................................................................... 4–11
Cycles Per Loop Iteration (CPLI) ................................................................................................. 4–11
Scheduling Information ................................................................................................................. 4–14
9.1
Altera Corporation