IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 19

• Manufacturer Part Number: IPTR-C2H-NIOS
• Description: IP CORE Renewal Of IPT-C2H-NIOS
• Manufacturer: Altera

Specifications of IPTR-C2H-NIOS

• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: Nios II
• Features: ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

C Code
Appropriate for
Hardware
Acceleration
Altera Corporation
November 2009
This section describes guidelines for identifying code that is appropriate
for the C2H Compiler.
Ideal Acceleration Candidates
Sections of C code that consume the most CPU time with the least amount
of code are excellent candidates for acceleration. These tend to have the
following characteristics:
■
■
Examples of such iterative tasks include memory copy-and-modify tasks,
checksum calculations, data encryption, decryption, and filtering
operations. In each of these cases, the C code iterates over a set of data
many times, with either one or more memory reads or writes performed
during each iteration.
Example 1–1
calculation. This code excerpt is from a TCP/IP stack, and it calculates the
checksum over ranges of data in a network protocol stack. Checksum
calculations are typically a time-consuming part of an IP stack, because all
data transmitted and received must be validated, which requires the
processor to loop through all bytes.
They contain a relatively small and simple loop or set of nested
loops.
They iterate over a set of data, performing one or more operations on
the data per iteration, and then store the result.
demonstrates a routine that performs a checksum
9.1
Introduction to the C2H Compiler
Nios II C2H Compiler User Guide
1–13