IPTR-C2H-NIOS Altera, IPTR-C2H-NIOS Datasheet - Page 62
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IPTR-C2H-NIOS
Manufacturer Part Number
IPTR-C2H-NIOS
Description
IP CORE Renewal Of IPT-C2H-NIOS
Manufacturer
Altera
Datasheet
1.IPT-C2H-NIOS.pdf
(138 pages)
Specifications of IPTR-C2H-NIOS
Software Application
IP CORE, NIOS Processor And Functions
Core Architecture
Nios II
Features
ANSI C Compliance, Straightforward C-to-Hardware Mapping, Reporting Of Generated Results
Core Sub-architecture
Cyclone
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Memory Accesses
Figure 3–10. Data Generation for a Write Operation
3–22
Nios II C2H Compiler User Guide
port. After some number of clock cycles determined by the slave memory
latency and arbitration delay, valid readdata returns to the master port.
(See section
Data Computation
For write operations to dereferenced pointers, data-computation logic in
the accelerator computes the value of the expression to write to memory.
This value is the write-data for an Avalon-MM master transfer to
memory. Data-computation logic operates in parallel with the address-
computation logic.
Consider the pointer dereference in the following code which performs a
write operation:
*(ptr_to_int + i) = x + y;
Figure 3–10
dereference for a write operation.
shows an example of the logic created for this pointer
“Read Operations with Latency” on page
9.1
3–37.)
Altera Corporation
November 2009
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