IPR-FIR Altera, IPR-FIR Datasheet - Page 6

IP CORE Renewal Of IP-FIR

IPR-FIR

Manufacturer Part Number
IPR-FIR
Description
IP CORE Renewal Of IP-FIR
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-FIR

Software Application
IP CORE, DSP Filters And Transforms
Supported Families
Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
Finite Impulse Response Compiler
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
1–2
Features
FIR Compiler User Guide
Table 1–3
device family.
Table 1–3. Device Family Support
The Altera
function and supports the following features:
Arria
Arria II GX
Arria II GZ
Cyclone
Cyclone II
Cyclone III
Cyclone III LS
Cyclone IV
HardCopy
HardCopy III
HardCopy IV E
HardCopy IV GX
Stratix
Stratix II
Stratix II GX
Stratix III
Stratix IV GT
Stratix IV GX/E
Stratix V
Stratix GX
Other device families
The following hardware architectures are supported to enable optimal trade- offs
between logic, memory, DSP blocks, and performance:
Exploit maximal efficiency designs as a result of FIR Compiler hardware
optimizations such as interpolation, decimation, symmetry, decimation half-band,
and time sharing.
Easy system integration using Avalon
GX
®
Fully parallel distributed arithmetic
Fully serial distributed arithmetic
Multibit serial distributed arithmetic
Multicycle variable structures
®
®
shows the level of support offered by the FIR Compiler to each Altera
II
®
FIR Compiler implements a finite impulse response (FIR) filter MegaCore
Device Family
®
Streaming (Avalon-ST) interfaces.
Final
Preliminary
Preliminary
Final
Final
Final
Preliminary
Preliminary
HardCopy Compilation
HardCopy Companion
HardCopy Companion
HardCopy Companion
Final
Final
Final
Final
Final
Final
Preliminary
Final
No support
© December 2010 Altera Corporation
Support
Chapter 1: About This Compiler
Features

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