IPR-FIR Altera, IPR-FIR Datasheet - Page 39

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Specify the Architecture Specification
Figure 3–9. Specify the Filter Architecture
© December 2010 Altera Corporation
1. For this tutorial, select Distributed Arithmetic: Fully Parallel Filter structure with
2. Click Finish when you have set the architecture parameters.
a pipeline level of 3.
Although these settings create a filter that uses a large number of logic cells,
increasing the pipeline level to 3 decreases the number of clock cycles to one,
thereby greatly increasing system performance. These settings are shown in
Figure
3–9.
FIR Compiler User Guide
3–15