IPR-FIR Altera, IPR-FIR Datasheet - Page 10

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–6
MegaCore Verification
Performance and Resource Utilization
Table 1–5. FIR Compiler Performance—Cyclone III Devices (Part 1 of 2)
FIR Compiler User Guide
Combinational
Multibit Serial, pipeline level 1 (2),
Multicycle variable (1 cycle) decimation by 4, pipeline level 1 (2),
Multicycle variable (1 cycle) interpolation by 4, pipeline level 2
Multicycle variable (1 cycle), pipeline level 2 (2),
Multicycle variable (4 cycle), pipeline level 2 (2),
1,528
2,543
1,182
LUTs
899
857
1
Registers
Logic
1,331
1,336
2,657
4,837
1,715
Before releasing an updated version of the FIR Compiler, Altera runs a comprehensive
regression test to verify its quality and correctness.
All features and architectures are tested by sweeping all parameter options and
verifying that the simulation matches a master functional model.
This section shows typical expected performance for a FIR Compiler MegaCore
function with Cyclone III and Stratix IV devices. All figures are given for a FIR filter
with 97 taps, 8-bit input data, 14-bit coefficients, a target f
Cyclone III devices use combinational look-up tables (LUTs) and logic registers;
Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logic
registers.
The resource and performance data was generated with the source ready signal
(ast_source_ready) always driven high, as described in
Interface” on page
Table 1–5
shows performance figures for Cyclone III devices:
(3)
55,148
1,158
Bits
578
66
92
Memory
4–13.
(4)
(3)
(6)
M9K
31
12
1
1
9
(4)
Multipliers
(3)
(9x9)
—
26
50
98
26
(MHz)
310
281
290
280
283
f
max
MAX
© December 2010 Altera Corporation
“Avalon Streaming
Throughput
set to 1 GHz.
Chapter 1: About This Compiler
(MSPS)
281
290
280
62
71
MegaCore Verification
(GMACs)
Processing
Equivalent
27
28
27
6
7
(1)