IPR-FIR Altera, IPR-FIR Datasheet - Page 41
![IP CORE Renewal Of IP-FIR](/photos/24/19/241940/4696153_sml.jpg)
IPR-FIR
Manufacturer Part Number
IPR-FIR
Description
IP CORE Renewal Of IP-FIR
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-FIR
Software Application
IP CORE, DSP Filters And Transforms
Supported Families
Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
Finite Impulse Response Compiler
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
Chapter 3: Parameter Settings
Filter Design Tips
© December 2010 Altera Corporation
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When importing floating-point coefficients, you should apply a scaling factor to
generate fixed-point integer numbers. Because coefficients are rounded to the
nearest integer, the scaling (or gain) factor can be set to zero—i.e., if it is too small.
If you do not scale the coefficients appropriately, you may have a filter with many
zeros.
The highest throughput filters are parallel filters with extended pipelining that
generate an output for every clock cycle.
Altera recommends that you use memory blocks to reduce the area.
The FIR filter typically runs at a higher f
Standard Fit (highest effort) is recommended for the fitter settings in the Quartus II
software to achieve optimum synthesis results.
To enable the decimation half-band optimized architecture, data storage and
coefficient storage should be set to either Auto or one of the available block
memories. Then select the filter tap value to be an odd number. The coefficient set
should be symmetric and every other coefficient value should be 0.
To enable the symmetric-interpolation optimized architecture, data storage and
coefficient storage should be set to either Auto or one of the available block
memories. The number of taps should be an odd value. Currently only even
symmetry is supported.
max
if the following constraints are set:
FIR Compiler User Guide
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