IPR-FIR Altera, IPR-FIR Datasheet - Page 58

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–16
Signals
Table 4–3.
FIR Compiler User Guide
clk
enable
reset_n
ast_sink_ready
ast_sink_valid
ast_sink_data
ast_sink_sop
ast_sink_eop
ast_sink_error
ast_source_ready
ast_source_valid
Signal
FIR Compiler Signals (Part 1 of 2)
1
The data transfer in
and valid are asserted. During cycle 1, startofpacket is asserted, and the first
data is transferred. During cycle 5, endofpacket is asserted indicating that this is the
end of the packet.
The channel signal indicates the channel index associated with the data. For
example, on cycle 1, the data D
The error signal stays at value 00 during a normal operation. Whenever a value
other than 00 is received from the data source (as in
detected by the Avalon-ST controller of the FIR filter, the controller is reset and waits
for the next valid startofpacket signal. It also transmits the received error signal
from its data source module error output.
The error signal only resets the Avalon-ST controller and not the design. Therefore,
the output data produced after an error condition may contain invalid data for several
cycles. It is recommended that a global reset is applied whenever an error message is
present in the system.
Table 4–3
Direction
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Output
lists the input and output signals for the FIR Compiler MegaCore function.
Clock signal used to clock all internal FIR filter registers.
Active high clock enable signal. This pin appears when the Add global clock
enable pin option is selected on the Parameterize FIR Compiler page. (The
Avalon-ST registers are NOT connected to this clock enable.)
Synchronous active low reset signal. Resets the FIR filter control circuit on the
rising edge of clk. This signal should last longer than one clock cycle.
Asserted by the FIR filter when it is able to accept data in the current clock cycle.
Asserted when input data is valid. When ast_sink_valid is not asserted, the
FIR processing is stopped if new data is required and no data is left in the Avalon-
ST input FIFO. Otherwise, the FIR processing continues.
Sample input data.
Marks the start of the incoming sample group. The start of packet (SOP) is
interpreted as a sample from channel 0.
Marks the end of the incoming sample group. If there is data associated with N
channels, the end of packet (EOP) must be high when the sample belonging to the
last channel (that is, channel N-1), is presented at the data input.
Error signal indicating Avalon-ST protocol violations on the sink side:
■
■
■
■
Other types of errors are also marked as 11.
Asserted by the downstream module if it is able to accept data.
Asserted by the FIR filter when there is valid data to output.
00: No error
01: Missing SOP
10: Missing EOP
11: Unexpected EOP
Figure 4–13
0
associated with channel 0 is available.
occurs on cycles 1, 2, 4, and five, when both ready
Description
Figure
© December 2010 Altera Corporation
4–11), or a packet error is
Chapter 4: Functional Description
Signals