IPR-FIR Altera, IPR-FIR Datasheet - Page 59

• Manufacturer Part Number: IPR-FIR
• Description: IP CORE Renewal Of IP-FIR
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FIR

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Arria II GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Finite Impulse Response Compiler
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Timing Diagrams
Table 4–3.
Timing Diagrams
© December 2010 Altera Corporation
ast_source_channel Output
ast_source_data
ast_source_sop
ast_source_eop
ast_source_error
coef_set
coef_in_clk
coef_set_in
coef_in
coef_we
coef_ld
FIR Compiler Signals (Part 2 of 2)
The reset_n signal resets the control logic and state machines that control the FIR
Compiler (not including data storage elements that hold previous inputs used to
calculate the result).
The previous data is not cleared when the reset_n signal is applied. To clear the
data, set the ast_sink_data port to 0 for n clock cycles, where n = (number of
coefficients) × (number of input channels) × (number of clock cycles needed to compute a FIR
result).
The FIR output value depends on the coefficient values in the design. Therefore, the
timing diagrams of your own design may be different than those shown in the
following figures. However, you can use the testbench generated by the FIR compiler
to get the correct timing relation between signals for a specific parameterized case.
All timing diagrams assume a full streaming operation where ast_source_ready
and ast_sink_ready are always 1 (unless otherwise stated).
Output
Output
Output
Output
Input
Input
Input
Input
Input
Output
Indicates the index of the channel whose result is presented at the data output.
The width of this signal = log
Filter output. The data width depends on the parameter settings.
Marks the start of the outgoing FIR filter result group. If '1', a result
corresponding to channel 0 is output.
Marks the end of the outgoing FIR filter result group. If '1', a result corresponding
to channel N-1 is output, where N is the number of channels.
Error signal indicating Avalon-ST protocol violations on the source side:
■
■
■
■
Other types of errors are also marked as 11.
Selects which coefficient set the FIR filter uses for the calculation. (Appears when
multiple coefficient sets are used.) The width of this signal = log
coefficient sets).
Clock to reload coefficients when coefficients are stored in memory. (Appears
when the Coefficient Reload option is selected and the Use Single Clock option is
not selected) This clock can be different than clk.
Selects which coefficient set to be reloaded. (Appears when multiple coefficient
sets are used and the Coefficient Reload option is selected.) The width of this
signal = log
Input coefficient value when reloading coefficient. (Appears when the Coefficient
Reload option is selected)
Active high write enable signal. Enables coefficient overwriting when coefficients
are reloadable.
Coefficient reload control port. This port is created only when multicycle filters are
selected and the coefficient storage is logic cells.
00: No error
01: Missing SOP
10: Missing EOP
11: Unexpected EOP
2
(number of coefficient sets)
2
(number of channels).
FIR Compiler User Guide
2
(number of
4–17