IPR-CRC Altera, IPR-CRC Datasheet - Page 7

• Manufacturer Part Number: IPR-CRC
• Description: IP CORE Renewal Of IP-CRC
• Manufacturer: Altera

Specifications of IPR-CRC

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 1: About This Compiler
General Description
General Description
CRC MegaCore Function Verification
Performance and Resource Utilization
Table 1–3. Performance and Resource Utilization for Cyclone II, Cyclone III and Stratix GX
© November 2009 Altera Corporation
Note to
(1) Parameters set to their default values are not mentioned.
Speed Grade
Device and
Cyclone III
Cyclone II
Stratix GX
Table
-6
-6
-5
1–3:
CRC generator
CRC generator
CRC checker
MegaCore
The CRC Compiler generates high-performance circuits to generate or check Cyclic
Redundancy Check (CRC) checksums for packet-based communication.
The CRC generator uses an Avalon-ST interface to receive data and emits generated
checksums on a dedicated output. The CRC checker similarly uses an Avalon-ST
interface to receive a packet with a CRC checksum and uses a dedicated output to
indicate if the checksum is correct. The CRC generator and checker MegaCore
functions do not store any data, checksums, or status.
Before releasing the CRC Compiler, Altera runs comprehensive regression tests to
verify the quality and correctness of the CRC Compiler.
Custom variations generated by the CRC Compiler exercise the CRC compiler’s
various parameter options. The resulting simulation models are thoroughly
simulated, and the results are verified against bit-accurate master simulation models.
Parameterization allows you to generate the most efficient implementation that meets
your design functionality, size, and performance goals.
The section lists the performance and resource utilization for several sample
implementations in different device families. The performance metrics were
generated using the Quartus
analyzer, with the fastest speed grade selected for the device family. Neither the
generator nor checker MegaCore function uses any memory.
Table 1–3
Cyclone II, Cyclone III, and Stratix GX devices.
Function
shows the typical expected performance and resource utilization for
8-bit datapath
1 symbol per word
Inputs and outputs not registered
CRC-16-CCITT
Optimize for area
16-bit datapath
2 symbols per word
CRC-16-ANSI
Optimize for speed
Parameter Settings
Preliminary
®
II software version 8.0 and the TimeQuest timing
(1)
Elements
Logic
147
34
34
420.17
450.05
MHz
277
f
max
CRC Compiler User Guide
Throughput
Gbps
3.36
3.6
4.4
1–3